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公开(公告)号:US20220415867A1
公开(公告)日:2022-12-29
申请号:US17735536
申请日:2022-05-03
发明人: Hsien-Wei CHEN , Shin-Puu JENG
IPC分类号: H01L25/10 , H01L25/065 , H01L25/00 , H01L23/498 , H01L23/14 , H01L23/538 , H01L23/64
摘要: Various disclosed embodiments include a substrate, a first interposer coupled to the substrate and to a first semiconductor device die, and a second interposer coupled to the substrate and to a second semiconductor device die. The first semiconductor device die may be a serializer/de-serializer die and the first semiconductor device die coupled to the first interposer may be located proximate to a sidewall of the substrate. In certain embodiments, the second semiconductor device die may be a system-on-chip die. In further embodiments, the second interposer may also be coupled to high bandwidth memory die. Placing a serializer/de-serializer die proximate to a sidewall of a substrate allows a length of electrical pathways to be reduced, thus reducing impedance and RC delay. The use of smaller, separate, interposers also reduces complexity of fabrication of interposers and similarly lowers impedance associated with redistribution interconnect structures associated with the interposers.
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2.
公开(公告)号:US20230380126A1
公开(公告)日:2023-11-23
申请号:US18230782
申请日:2023-08-07
发明人: Ming-Chih YEW , Shu-Shen YEH , Chin-Hua WANG , Po-Yao LIN , Shin-Puu JENG
IPC分类号: H10B10/00 , H01L21/56 , H01L23/528 , H01L23/535 , H01L23/538 , H01L23/00 , H01L25/065
CPC分类号: H10B10/00 , H01L21/563 , H01L23/5283 , H01L23/535 , H01L23/5386 , H01L24/09 , H01L24/32 , H01L25/0655 , H01L2224/02379 , H01L2224/32137
摘要: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.
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3.
公开(公告)号:US20230307337A1
公开(公告)日:2023-09-28
申请号:US17701737
申请日:2022-03-23
发明人: Hsien-Wei CHEN , Jing-Ye JUANG , Shin-Puu JENG
IPC分类号: H01L23/498 , H01L25/16 , H01L25/065 , H01L21/48 , H01L23/00
CPC分类号: H01L23/49822 , H01L25/162 , H01L25/0655 , H01L21/486 , H01L21/4857 , H01L24/73 , H01L24/16 , H01L24/32 , H01L23/49816 , H01L23/49838 , H01L23/49833 , H01L23/49894 , H01L2924/1434 , H01L2224/73204 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225
摘要: A package assembly includes a package substrate including a molding material layer and a plurality of substrate portions embedded in the molding material layer, a redistribution layer (RDL) structure on the package substrate, and a plurality of semiconductor devices on the RDL structure.
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公开(公告)号:US20230352381A1
公开(公告)日:2023-11-02
申请号:US17730410
申请日:2022-04-27
发明人: Li-Ling LIAO , Ming-Chih YEW , Chia-Kuei HSU , Po-Yao LIN , Shin-Puu JENG
IPC分类号: H01L23/498 , H01L25/065 , H01L21/48
CPC分类号: H01L23/49816 , H01L25/0652 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L21/4853 , H01L2924/3841 , H01L2924/3512 , H01L2924/3511 , H01L2924/1437 , H01L2924/1432 , H01L25/0657 , H01L24/73
摘要: A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.
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5.
公开(公告)号:US20230063304A1
公开(公告)日:2023-03-02
申请号:US17462057
申请日:2021-08-31
发明人: Monsen LIU , Shuo-Mao CHEN , Po-Ying LAI , Shang-Lun TSAI , Shin-Puu JENG
IPC分类号: H01L23/498 , H01L23/14 , H01L23/15 , H01L21/48
摘要: Devices and methods of manufacture for a hybrid interposer within a semiconductor device. A semiconductor device may include a package substrate and a hybrid interposer. The hybrid interposer may include an organic interposer material layer, and a non-organic interposer material layer positioned between the organic interposer material layer and the package substrate. The semiconductor device may further include an integrated device positioned within the hybrid interposer. In one embodiment, the integrated device may be positioned within the organic interposer material layer. In another embodiment, the integrated device may be positioned within the non-organic interposer material layer. In a further embodiment, the integrated device may be positioned within the organic interposer material layer and the non-organic interposer material layer.
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公开(公告)号:US20230023380A1
公开(公告)日:2023-01-26
申请号:US17859038
申请日:2022-07-07
发明人: Chia-Kuei HSU , Ming-Chih YEW , Shu-Shen YEH , Po-Yao LIN , Shin-Puu JENG
IPC分类号: H01L23/498 , H01L25/065 , H01L21/48 , H01L21/56
摘要: A semiconductor structure includes a fan-out package, a packaging substrate, an solder material portions bonded to the fan-out package and the packaging substrate, an underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the underfill material portion and having a Young's modulus is lower than a Young's modulus of the underfill material portion.
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公开(公告)号:US20220406671A1
公开(公告)日:2022-12-22
申请号:US17523955
申请日:2021-11-11
发明人: Chia-Kuei HSU , Ming-Chih YEW , Shu-Shen YEH , Po-Yao LIN , Shin-Puu JENG
摘要: A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.
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8.
公开(公告)号:US20240321717A1
公开(公告)日:2024-09-26
申请号:US18731407
申请日:2024-06-03
发明人: Li-Ling LIAO , Ming-Chih YEW , Chia-Kuei HSU , Shu-Shen YEH , Po-Yao LIN , Shin-Puu JENG
IPC分类号: H01L23/498 , H10K71/00
CPC分类号: H01L23/49838 , H01L23/49805 , H01L23/49822 , H10K71/621 , H01L23/49816
摘要: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
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公开(公告)号:US20240274577A1
公开(公告)日:2024-08-15
申请号:US18641643
申请日:2024-04-22
发明人: Chin-Hua WANG , Po-Chen LAI , Shu-Shen YEH , Tsung-Yen LEE , Po-Yao LIN , Shin-Puu JENG
IPC分类号: H01L25/065 , H01L23/373 , H01L23/498 , H01L25/00
CPC分类号: H01L25/0655 , H01L23/3731 , H01L23/49822 , H01L25/50
摘要: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
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公开(公告)号:US20230260963A1
公开(公告)日:2023-08-17
申请号:US18138201
申请日:2023-04-24
发明人: Chin-Hua WANG , Po-Chen LAI , Shu-Shen YEH , Tsung-Yen LEE , Po-Yao LIN , Shin-Puu JENG
IPC分类号: H01L25/065 , H01L25/00 , H01L23/498 , H01L23/373
CPC分类号: H01L25/0655 , H01L25/50 , H01L23/49822 , H01L23/3731
摘要: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
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