公开(公告)号：US10164018B1

公开(公告)日：2018-12-25

申请号：US15675535

申请日：2017-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ching-Fu Yeh ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L45/00 ,  H01L29/16 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US10163753B2

公开(公告)日：2018-12-25

申请号：US15651834

申请日：2017-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer.

公开(公告)号：US10000373B2

公开(公告)日：2018-06-19

申请号：US15007852

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Carlos H. Diaz ,  Ken-Ichi Goto ,  Shau-Lin Shue ,  Tai-I Yang

IPC: H04R23/00 ,  B81B3/00 ,  B81C1/00

CPC classification number: B82B1/005 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/09 ,  B81C1/00246 ,  B81C2203/0136 ,  B81C2203/0771 ,  B82B3/008

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a substrate and an interconnect structure formed over the substrate. The NEMS device structure includes a dielectric layer formed over the interconnect structure and a beam structure formed in and over the dielectric layer. The beam structure includes a fixed portion and a moveable portion, the fixed portion is extended vertically, and the movable portion is extended horizontally. The NEMS device structure includes a cap structure formed over the dielectric layer and the beam structure and a cavity formed between the beam structure and the cap structure.

公开(公告)号：US20240153870A1

公开(公告)日：2024-05-09

申请号：US18413426

申请日：2024-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsien Peng ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/28556 ,  H01L21/32139 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/53238

Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.

公开(公告)号：US11967552B2

公开(公告)日：2024-04-23

申请号：US17402942

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252

Abstract: A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.

公开(公告)号：US11948834B2

公开(公告)日：2024-04-02

申请号：US17671222

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0228 ,  H01L21/30604 ,  H01L21/31116

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

公开(公告)号：US11894266B2

公开(公告)日：2024-02-06

申请号：US18064561

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/76 ,  H01L21/32 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321

CPC classification number: H01L21/7685 ,  H01L21/02118 ,  H01L21/28568 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/53266

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US11769695B2

公开(公告)日：2023-09-26

申请号：US17181427

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Chia-Tien Wu ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L21/76885 ,  H01L21/7684 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76886 ,  H01L23/528 ,  H01L29/45

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

公开(公告)号：US11594483B2

公开(公告)日：2023-02-28

申请号：US16714444

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor structure includes a semiconductor substrate, a via, a first dielectric layer, a first graphene layer, a metal line, and a second graphene layer. The via is over the semiconductor substrate. The first dielectric layer laterally surrounds the via. The first graphene layer extends along a top surface of the via. The metal line is over the via and is in contact with the first graphene layer. The second graphene layer peripherally encloses the metal line and the first graphene layer.

公开(公告)号：US20220367346A1

公开(公告)日：2022-11-17

申请号：US17873590

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.