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公开(公告)号：US09728503B2
公开(公告)日：2017-08-08
申请号：US14926469
申请日：2015-10-29
发明人： Chao-Hsien Peng , Chi-Liang Kuo , Ming-Han Lee , Hsiang-Huan Lee , Shau-Lin Shue
IPC分类号： H01L21/00 , H01L23/00 , H01L23/532 , H01L23/522 , H01L21/768 , H01L23/528
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76855 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53223 , H01L23/53252 , H01L23/53261 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
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公开(公告)号：US20160049373A1
公开(公告)日：2016-02-18
申请号：US14926469
申请日：2015-10-29
发明人： Chao-Hsien Peng , Chi-Liang Kuo , Ming-Han Lee , Hsiang-Huan Lee , Shau-Lin Shue
IPC分类号： H01L23/532 , H01L23/522 , H01L23/528 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76855 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53223 , H01L23/53252 , H01L23/53261 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
摘要翻译： 在一些实施例中，本公开涉及导电互连层。 导电互连层具有设置在基板上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。
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公开(公告)号：US20240153870A1
公开(公告)日：2024-05-09
申请号：US18413426
申请日：2024-01-16
发明人： Chao-Hsien Peng , Hsiang-Huan Lee , Shau-Lin Shue
IPC分类号： H01L23/522 , H01L21/285 , H01L21/3213 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/28556 , H01L21/32139 , H01L21/76879 , H01L21/76885 , H01L23/53238
摘要： A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.
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公开(公告)号：US09219033B2
公开(公告)日：2015-12-22
申请号：US14221509
申请日：2014-03-21
发明人： Chao-Hsien Peng , Chi-Liang Kuo , Ming-Han Lee , Hsiang-Huan Lee , Shau-Lin Shue
IPC分类号： H01L23/522 , H01L21/00 , H01L23/528 , H01L23/532 , H01L21/768 , H01L21/285 , H01L21/288
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76855 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53223 , H01L23/53252 , H01L23/53261 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
摘要翻译： 本公开内容涉及使用预填充工艺形成以减少空隙的金属互连层，以及相关联的方法。 在一些实施例中，金属互连层具有设置在衬底上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。
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公开(公告)号：US20150270215A1
公开(公告)日：2015-09-24
申请号：US14221509
申请日：2014-03-21
发明人： Chao-Hsien Peng , Chi-Liang Kuo , Ming-Han Lee , Hsiang-Huan Lee , Shau-Lin Shue
IPC分类号： H01L23/522 , H01L21/288 , H01L21/768 , H01L21/285 , H01L23/528 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76855 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53223 , H01L23/53252 , H01L23/53261 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
摘要翻译： 本公开内容涉及使用预填充工艺形成以减少空隙的金属互连层，以及相关联的方法。 在一些实施例中，金属互连层具有设置在衬底上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。
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