公开(公告)号：US10651279B2

公开(公告)日：2020-05-12

申请号：US16227592

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ching-Fu Yeh ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L29/16 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US20150255334A1

公开(公告)日：2015-09-10

申请号：US14720264

申请日：2015-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ching-Fu Yeh ,  Tz-Jun Kuo ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC: H01L21/768

CPC classification number: H01L21/76873 ,  C25D3/38 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/44 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879

Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Abstract translation: 这里提出的是一种电镀方法，包括提供一个具有形成在一个迹线上的电介质层的衬底，以及形成延伸穿过该电介质层的通孔/沟槽开口，该通孔/沟槽开口暴露该迹线的表面。 该方法还包括在通孔/沟槽开口中形成种子层并与迹线接触并在种子层上形成保护层。 去除保护层，并通过在通孔/沟槽开口中施加电镀溶液，在单个电镀工艺步骤中在种子层上沉积导电层。

公开(公告)号：US09966304B2

公开(公告)日：2018-05-08

申请号：US15263249

申请日：2016-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Ching-Fu Yeh ,  Hsin-Chen Tsai ,  Yao-Hsiang Liang ,  Yu-Min Chang ,  Shih-Chi Lin

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

公开(公告)号：US09324608B2

公开(公告)日：2016-04-26

申请号：US14720264

申请日：2015-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ching-Fu Yeh ,  Tz-Jun Kuo ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L21/76873 ,  C25D3/38 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/44 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879

Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

公开(公告)号：US10164018B1

公开(公告)日：2018-12-25

申请号：US15675535

申请日：2017-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ching-Fu Yeh ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L45/00 ,  H01L29/16 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US20150001720A1

公开(公告)日：2015-01-01

申请号：US13929341

申请日：2013-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Yu-Hung Lin ,  Ching-Fu Yeh ,  Hsin-Chen Tsai ,  Yao-Hsiang Liang ,  Yu-Min Chang ,  Shih-Chi Lin

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

Abstract translation: 公开了改进的互连结构和用于形成互连结构的方法，其允许互连结构实现较低的Rc。 为了降低互连结构的Rc，将α相诱导金属层引入到第一Ta阻挡层上。 以诱导其后的Ta沉积到α相Ta势垒层的形成中。 具有α相的主结晶结构的随后沉积的Ta阻挡层具有比第二相Ta层阻挡层低的Rc。