公开(公告)号：US11854874B2

公开(公告)日：2023-12-26

申请号：US17086754

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522

CPC classification number: H01L21/76858 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2221/1073 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US11749603B2

公开(公告)日：2023-09-05

申请号：US17811649

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L31/062 ,  H01L31/113 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/3065 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/485 ,  H01L23/528 ,  H01L23/535 ,  H01L23/53266 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

公开(公告)号：US20220344274A1

公开(公告)日：2022-10-27

申请号：US17811649

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/3065 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

公开(公告)号：US20210281037A1

公开(公告)日：2021-09-09

申请号：US17240620

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chia-Nan Yuan ,  Shih-Guo Shen ,  Der-Chyang Yeh ,  Yu-Hung Lin ,  Ming Shih Yeh

IPC: H01S5/02 ,  H01S5/30 ,  H01S5/026 ,  H01S5/323 ,  H01S5/042 ,  H01S5/0234 ,  H01S5/0237 ,  H01S5/02234

Abstract: In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

公开(公告)号：US09966304B2

公开(公告)日：2018-05-08

申请号：US15263249

申请日：2016-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Ching-Fu Yeh ,  Hsin-Chen Tsai ,  Yao-Hsiang Liang ,  Yu-Min Chang ,  Shih-Chi Lin

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

公开(公告)号：US11450612B2

公开(公告)日：2022-09-20

申请号：US16924201

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  An-Jhih Su ,  Der-Chyang Yeh ,  Shih-Guo Shen ,  Chia-Nan Yuan ,  Ming-Shih Yeh

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

公开(公告)号：US09793204B2

公开(公告)日：2017-10-17

申请号：US15065800

申请日：2016-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Chun-Hsien Huang ,  I-Tseng Chen

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.

公开(公告)号：US09721896B2

公开(公告)日：2017-08-01

申请号：US14992997

申请日：2016-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53266

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

公开(公告)号：US20150001720A1

公开(公告)日：2015-01-01

申请号：US13929341

申请日：2013-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Yu-Hung Lin ,  Ching-Fu Yeh ,  Hsin-Chen Tsai ,  Yao-Hsiang Liang ,  Yu-Min Chang ,  Shih-Chi Lin

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

Abstract translation: 公开了改进的互连结构和用于形成互连结构的方法，其允许互连结构实现较低的Rc。 为了降低互连结构的Rc，将α相诱导金属层引入到第一Ta阻挡层上。 以诱导其后的Ta沉积到α相Ta势垒层的形成中。 具有α相的主结晶结构的随后沉积的Ta阻挡层具有比第二相Ta层阻挡层低的Rc。

公开(公告)号：US20240319590A1

公开(公告)日：2024-09-26

申请号：US18186413

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Yu-Yi Huang ,  Chih-Hao Yu ,  Yu-Ting Yen ,  Shih-Peng Tai

IPC: G03F7/00 ,  G03F7/075 ,  G03F7/09 ,  G03F7/16

CPC classification number: G03F7/0005 ,  G03F7/0757 ,  G03F7/091 ,  G03F7/167 ,  G03F7/7015

Abstract: Optical devices and methods of manufacture are presented in which a first mask is utilized for multiple purposes. Some methods include depositing a first mask over a support material, forming a concave surface in the support material through the first mask, and bonding the first mask to a first bonding layer over an optical interposer.