公开(公告)号：US11670553B2

公开(公告)日：2023-06-06

申请号：US17397529

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/324

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/324 ,  H01L21/76832 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US09287153B2

公开(公告)日：2016-03-15

申请号：US14461035

申请日：2014-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Kai Chen ,  Hung-Chih Wang ,  Hon-Lin Huang ,  Shih-Chi Lin

IPC: B05D3/06 ,  H01L21/677 ,  H01L21/67 ,  C30B25/10

CPC classification number: H01L21/67167 ,  C30B25/105 ,  C30B29/06 ,  C30B33/02 ,  C30B35/00 ,  H01L21/67098

Abstract: A semiconductor baking apparatus includes a load lock chamber, a process chamber, a transfer chamber, a first interior door, and a controller. The process chamber has a first accommodating space therein. The transfer chamber has a second accommodating space therein, and the transfer chamber is connected to the load lock chamber and the process chamber. The first interior door is between the process chamber and the transfer chamber. When the first interior door is opened, the first accommodating space is communicated with the second accommodating space. The controller is programmed to open the first interior door when the semiconductor baking apparatus idles.

Abstract translation: 半导体烘烤装置包括负载锁定室，处理室，传送室，第一室内门和控制器。 处理室在其中具有第一容纳空间。 传送室在其中具有第二容纳空间，并且传送室连接到负载锁定室和处理室。 第一内门位于处理室和传送室之间。 当第一内门打开时，第一容纳空间与第二容纳空间连通。 当半导体烘烤设备闲置时，控制器被编程为打开第一内门。

公开(公告)号：US20230268231A1

公开(公告)日：2023-08-24

申请号：US18309416

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash SAVANT ,  Chia-Ming TSAI ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/324

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/28088 ,  H01L21/28158 ,  H01L29/66795 ,  H01L21/76832 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/4966 ,  H01L21/324 ,  H01L21/823462

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US09966304B2

公开(公告)日：2018-05-08

申请号：US15263249

申请日：2016-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Ching-Fu Yeh ,  Hsin-Chen Tsai ,  Yao-Hsiang Liang ,  Yu-Min Chang ,  Shih-Chi Lin

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

公开(公告)号：US12300549B2

公开(公告)日：2025-05-13

申请号：US18309416

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/324 ,  H01L21/768 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US20210366778A1

公开(公告)日：2021-11-25

申请号：US17397529

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/324

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US09601593B2

公开(公告)日：2017-03-21

申请号：US14455512

申请日：2014-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Ke-Chih Liu ,  Chia-Ming Tsai ,  Shih-Chi Lin

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165 ,  H01L21/285

CPC classification number: H01L29/6656 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.

公开(公告)号：US20250014946A1

公开(公告)日：2025-01-09

申请号：US18348967

申请日：2023-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fan Hsuan Chien ,  Su-Yu Yeh ,  Teng-Ta Hung ,  Chun-Jen Chen ,  Pei Yen Cheng ,  Shih-Chi Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A method includes etching a gate stack to form a trench extending through the gate stack, the gate stack including a metal gate electrode and a gate dielectric, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion; extending the trench through an isolation region under the gate stack and into a semiconductor substrate under the isolation region; conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.

公开(公告)号：US11088029B2

公开(公告)日：2021-08-10

申请号：US16376432

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/324

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US20150001720A1

公开(公告)日：2015-01-01

申请号：US13929341

申请日：2013-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Yu-Hung Lin ,  Ching-Fu Yeh ,  Hsin-Chen Tsai ,  Yao-Hsiang Liang ,  Yu-Min Chang ,  Shih-Chi Lin

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

Abstract translation: 公开了改进的互连结构和用于形成互连结构的方法，其允许互连结构实现较低的Rc。 为了降低互连结构的Rc，将α相诱导金属层引入到第一Ta阻挡层上。 以诱导其后的Ta沉积到α相Ta势垒层的形成中。 具有α相的主结晶结构的随后沉积的Ta阻挡层具有比第二相Ta层阻挡层低的Rc。