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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES
    2.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210272955A1

    公开(公告)日：2021-09-02

    申请号：US16934916

    申请日：2020-07-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shahaji B. MORE ,  Chandrashekhar Prakash SAVANT ,  Tien-Wei YU ,  Chia-Ming TSAI

    IPC: H01L27/092 ,  H01L21/8238

    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

    METHOD FOR FORMING GATE DIELECTRIC LAYER
    4.
    发明申请
    METHOD FOR FORMING GATE DIELECTRIC LAYER 审中-公开
    形成栅介质层的方法

    公开(公告)号：US20150287605A1

    公开(公告)日：2015-10-08

    申请号：US14743419

    申请日：2015-06-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Liang-Chen CHI ,  Chia-Ming TSAI ,  Chin-Kun WANG ,  Jhih-Jie HUANG ,  Miin-Jang CHEN

    IPC: H01L21/28

    CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/785

    Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate. The method includes forming a buffer layer over the semiconductor substrate. The buffer layer is in an amorphous state. The method includes nitriding the buffer layer into a nitride buffer layer. The method includes forming a gate dielectric layer over the nitride buffer layer. The method includes performing a thermal annealing process to convert the gate dielectric layer into a crystalline gate dielectric layer. The method includes forming a gate electrode over the crystalline gate dielectric layer.

    Abstract translation: 提供一种形成半导体器件的方法。 该方法包括提供半导体衬底。 该方法包括在半导体衬底上形成缓冲层。 缓冲层处于非晶状态。 该方法包括将缓冲层氮化成氮化物缓冲层。 该方法包括在氮化物缓冲层上形成栅介质层。 该方法包括执行热退火工艺以将栅极电介质层转换成结晶栅极电介质层。 该方法包括在晶体栅介电层上形成栅电极。

    DOPANT PROFILE CONTROL IN GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
    6.
    发明申请
    DOPANT PROFILE CONTROL IN GATE STRUCTURES FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210391220A1

    公开(公告)日：2021-12-16

    申请号：US16900054

    申请日：2020-06-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chandrashekhar Prakash SAVANT ,  Chia-Ming TSAI ,  Tien-Wei YU

    IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.

    TRENCH ISOLATION WITH CONDUCTIVE STRUCTURES
    8.
    发明申请
    TRENCH ISOLATION WITH CONDUCTIVE STRUCTURES 有权

    公开(公告)号：US20230005796A1

    公开(公告)日：2023-01-05

    申请号：US17815094

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chandrashekhar Prakash SAVANT ,  Chia-Ming TSAI ,  Yuh-Ta FAN ,  Tien-Wei YU

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/49

    Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES
    9.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220115521A1

    公开(公告)日：2022-04-14

    申请号：US17070232

    申请日：2020-10-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chandrashekhar Prakash SAVANT ,  Chia-Ming TSAI ,  Tien-Wei Yu

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

    Abstract: The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping and to form multiple devices with different Vt. The method includes forming a gate dielectric layer on a fin structure, forming a buffer layer on the gate dielectric layer, and forming a dopant source layer including a dopant on the buffer layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. The method further includes doping a portion of the high-k dielectric layer adjacent to the interfacial layer with the dopant, removing the dopant source layer and the buffer layer, forming a dopant pulling layer on the gate dielectric layer, and tuning the dopant in the gate dielectric layer by the dopant pulling layer.

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20210305411A1

    公开(公告)日：2021-09-30

    申请号：US16829614

    申请日：2020-03-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chandrashekhar P. SAVANT ,  Tien-Wei YU ,  Ke-Chih LIU ,  Chia-Ming TSAI

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/49 ,  H01L21/02

    Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.

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