公开(公告)号：US20230163187A1

公开(公告)日：2023-05-25

申请号：US18151575

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei WANG ,  Chia-Ming TSAI ,  Ke-Chih LIU ,  Chandrashekhar Prakash SAVANT ,  Tien-Wei YU

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/785 ,  H01L29/0649 ,  H01L21/823437 ,  H01L21/28088 ,  H01L27/0886 ,  H01L21/823431 ,  H01L29/66795

Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.

公开(公告)号：US20210020756A1

公开(公告)日：2021-01-21

申请号：US17063177

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei WANG ,  Chia-Ming TSAI ,  Ke-Chih LIU ,  Chandrashekhar Prakash SAVANT ,  Tien-Wei YU

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.

公开(公告)号：US20220320320A1

公开(公告)日：2022-10-06

申请号：US17843373

申请日：2022-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chandrashekhar P. SAVANT ,  Tien-Wei YU ,  Ke-Chih LIU ,  Chia-Ming TSAI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/49 ,  H01L29/40

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.

公开(公告)号：US20200105894A1

公开(公告)日：2020-04-02

申请号：US16438168

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei WANG ,  Chia-Ming TSAI ,  Ke-Chih LIU ,  Chandrashekhar Prakash SAVANT ,  Tien-Wei YU

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234

Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.

公开(公告)号：US20240097009A1

公开(公告)日：2024-03-21

申请号：US18522064

申请日：2023-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chandrashekhar P. SAVANT ,  Tien-Wei YU ,  Ke-Chih LIU ,  Chia-Ming TSAI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02186 ,  H01L21/0228 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. The channel region is over the substrate. The gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. The source/drain regions are at opposite sides of the channel region.

公开(公告)号：US20210305411A1

公开(公告)日：2021-09-30

申请号：US16829614

申请日：2020-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chandrashekhar P. SAVANT ,  Tien-Wei YU ,  Ke-Chih LIU ,  Chia-Ming TSAI

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/49 ,  H01L21/02

Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.

公开(公告)号：US20160043186A1

公开(公告)日：2016-02-11

申请号：US14455512

申请日：2014-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Chih LIU ,  Chia-Ming TSAI ,  Shih-Chi LIN

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括位于半导体衬底上的栅极堆叠。 栅极堆叠包括栅极电介质层和位于栅极电介质层上的栅电极。 半导体器件结构包括位于栅极堆叠的第一侧壁上方的间隔物。 间隔物和栅极堆叠围绕凹部。 半导体器件结构包括形成在半导体衬底上并围绕栅堆叠的绝缘层。 半导体器件结构包括覆盖绝缘层，间隔物和凹部的内壁的覆盖层。