公开(公告)号：US20160043186A1

公开(公告)日：2016-02-11

申请号：US14455512

申请日：2014-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Chih LIU ,  Chia-Ming TSAI ,  Shih-Chi LIN

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括位于半导体衬底上的栅极堆叠。 栅极堆叠包括栅极电介质层和位于栅极电介质层上的栅电极。 半导体器件结构包括位于栅极堆叠的第一侧壁上方的间隔物。 间隔物和栅极堆叠围绕凹部。 半导体器件结构包括形成在半导体衬底上并围绕栅堆叠的绝缘层。 半导体器件结构包括覆盖绝缘层，间隔物和凹部的内壁的覆盖层。

公开(公告)号：US20250022925A1

公开(公告)日：2025-01-16

申请号：US18221160

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fan Hsuan CHIEN ,  Kai-Shiung HSU ,  Shih-Chi LIN ,  Cheng-Han TSAI ,  Pei Yen CHENG

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, epitaxially growing a S/D region on the fin base, forming a contact opening on the S/D region, forming a semiconductor nitride layer on a sidewall of the contact opening, performing a densification process on the semiconductor nitride layer to form a densified semiconductor nitride layer, forming a silicide layer on an exposed surface of the S/D region in the contact opening, forming a contact plug in the contact opening, and forming a via structure in the contact plug.

公开(公告)号：US20160379875A1

公开(公告)日：2016-12-29

申请号：US15263249

申请日：2016-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung LIN ,  Ching-Fu YEH ,  Hsin-Chen TSAI ,  Yao-Hsiang LIANG ,  Yu-Min CHANG ,  Shih-Chi LIN

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

Abstract translation: 公开了改进的互连结构和用于形成互连结构的方法，其允许互连结构实现较低的Rc。 为了降低互连结构的Rc，在β相的第一Ta阻挡层上引入α相诱导金属层，以引起其后的Ta沉积形成α相Ta阻挡层。 具有α相的主晶体结构的随后沉积的Ta阻挡层具有比β相Ta阻挡层低的Rc。

公开(公告)号：US20160365343A1

公开(公告)日：2016-12-15

申请号：US14739379

申请日：2015-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Yu-Hung LIN ,  Hon-Lin HUANG ,  Rueijer LIN ,  Shih-Chi LIN ,  Sheng-Hsuan LIN

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6653

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a spacer on a sidewall of the gate structure. The method for manufacturing a semiconductor structure further includes forming a hard mask structure on a top surface of the gate structure and on an upper portion of the spacer but not on a bottom portion of the spacer.

Abstract translation: 提供半导体结构及其形成方法。 制造半导体结构的方法包括在衬底上形成栅极结构，并在栅极结构的侧壁上形成间隔物。 制造半导体结构的方法还包括在栅极结构的顶表面上和在间隔物的上部而不是在间隔物的底部上形成硬掩模结构。

公开(公告)号：US20160049321A1

公开(公告)日：2016-02-18

申请号：US14461035

申请日：2014-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Kai CHEN ,  Hung-Chih WANG ,  Hon-Lin HUANG ,  Shih-Chi LIN

IPC: H01L21/677 ,  H01L21/67

CPC classification number: H01L21/67167 ,  C30B25/105 ,  C30B29/06 ,  C30B33/02 ,  C30B35/00 ,  H01L21/67098

Abstract: A semiconductor baking apparatus includes a load lock chamber, a process chamber, a transfer chamber, a first interior door, and a controller. The process chamber has a first accommodating space therein. The transfer chamber has a second accommodating space therein, and the transfer chamber is connected to the load lock chamber and the process chamber. The first interior door is between the process chamber and the transfer chamber. When the first interior door is opened, the first accommodating space is communicated with the second accommodating space. The controller is programmed to open the first interior door when the semiconductor baking apparatus idles.

Abstract translation: 半导体烘烤装置包括负载锁定室，处理室，传送室，第一室内门和控制器。 处理室在其中具有第一容纳空间。 传送室在其中具有第二容纳空间，并且传送室连接到负载锁定室和处理室。 第一内门位于处理室和传送室之间。 当第一内门打开时，第一容纳空间与第二容纳空间连通。 当半导体烘烤设备闲置时，控制器被编程为打开第一内门。