公开(公告)号：US11670553B2

公开(公告)日：2023-06-06

申请号：US17397529

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/324

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/324 ,  H01L21/76832 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US11329160B2

公开(公告)日：2022-05-10

申请号：US15435168

申请日：2017-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Chung-Ren Sun ,  Ming-Te Chen ,  Ting-Chun Wang ,  Jun-Jie Cheng

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

公开(公告)号：US20230268231A1

公开(公告)日：2023-08-24

申请号：US18309416

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash SAVANT ,  Chia-Ming TSAI ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/324

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/28088 ,  H01L21/28158 ,  H01L29/66795 ,  H01L21/76832 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/4966 ,  H01L21/324 ,  H01L21/823462

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US11081584B2

公开(公告)日：2021-08-03

申请号：US16532274

申请日：2019-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chandrashekhar Prakash Savant ,  Kin Shun Chong ,  Tien-Wei Yu ,  Chia-Ming Tsai ,  Ming-Te Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

公开(公告)号：US09437433B2

公开(公告)日：2016-09-06

申请号：US14170837

申请日：2014-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Yuan Ho ,  Jung-Wei Lee ,  Ming-Te Chen

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/26593 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67201 ,  H01L21/67213 ,  H01L21/67745

Abstract: Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes placing the wafer in a process module. The method also includes performing the ion implantation process on the wafer and simultaneously cooling the wafer in the process module. The method further includes removing the wafer from the process module. In addition, the method includes heating up the wafer.

Abstract translation: 提供了在离子注入工艺中冷却晶片的方法的实施例。 用于在离子注入工艺中冷却晶片的方法包括将晶片放置在处理模块中。 该方法还包括在晶片上执行离子注入工艺并同时冷却处理模块中的晶片。 该方法还包括从处理模块移除晶片。 此外，该方法包括加热晶片。

公开(公告)号：US09589804B2

公开(公告)日：2017-03-07

申请号：US14814370

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Chung-Ren Sun ,  Ming-Te Chen ,  Ting-Chun Wang ,  Jun-Jie Cheng

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.

Abstract translation: 半导体器件包括半导体鳍片，衬里氧化物层，氮化硅基层和栅极氧化物层。 半导体翅片具有顶表面，与顶表面相邻的第一侧表面，以及设置在第一侧表面下方并与其邻近的第二侧表面。 衬里氧化物层周边地包围半导体鳍片的第二侧表面。 氮化硅基层与衬里氧化物层一致地设置。 栅极氧化物层与顶表面和第一侧表面共形设置。

公开(公告)号：US12300549B2

公开(公告)日：2025-05-13

申请号：US18309416

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/324 ,  H01L21/768 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US20210366778A1

公开(公告)日：2021-11-25

申请号：US17397529

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Shih-Chi Lin ,  Zack Chong ,  Tien-Wei Yu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/324

Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

公开(公告)号：US11232953B2

公开(公告)日：2022-01-25

申请号：US16573596

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Miao-Syuan Fan ,  Ching-Hua Lee ,  Ming-Te Chen ,  Jung-Wei Lee ,  Pei-Wei Lee

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

公开(公告)号：US11183431B2

公开(公告)日：2021-11-23

申请号：US16562395

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Tien-Wei Yu

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.