公开(公告)号：US09324608B2

公开(公告)日：2016-04-26

申请号：US14720264

申请日：2015-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ching-Fu Yeh ,  Tz-Jun Kuo ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/288

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/44 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879

摘要： Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

公开(公告)号：US20140231998A1

公开(公告)日：2014-08-21

申请号：US13771175

申请日：2013-02-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chi-Liang Kuo ,  Tz-Jun Kuo ,  Hsiang-Huan Lee

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76832 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

摘要翻译： 本公开涉及一种形成后端金属互连层的方法。 该方法通过在半导体衬底上沉积一个或多个自组装单层来限定金属互连层区域来进行。 在金属互连层区域内的半导体衬底上形成具有多个金属结构的金属互连层。 然后在多个金属结构之间的区域中在半导体衬底的表面上形成层间电介质层。

公开(公告)号：US20220262675A1

公开(公告)日：2022-08-18

申请号：US17734683

申请日：2022-05-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tz-Jun Kuo ,  Chien-Hsin HO ,  Ming-Han LEE

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US20150255334A1

公开(公告)日：2015-09-10

申请号：US14720264

申请日：2015-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ching-Fu Yeh ,  Tz-Jun Kuo ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/44 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879

摘要： Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

摘要翻译： 这里提出的是一种电镀方法，包括提供一个具有形成在一个迹线上的电介质层的衬底，以及形成延伸穿过该电介质层的通孔/沟槽开口，该通孔/沟槽开口暴露该迹线的表面。 该方法还包括在通孔/沟槽开口中形成种子层并与迹线接触并在种子层上形成保护层。 去除保护层，并通过在通孔/沟槽开口中施加电镀溶液，在单个电镀工艺步骤中在种子层上沉积导电层。

公开(公告)号：US11322391B2

公开(公告)日：2022-05-03

申请号：US16593562

申请日：2019-10-04

申请人： Taiwan Semiconductor Manufacturing, Co., Ltd.

发明人： Tz-Jun Kuo ,  Chien-Hsin Ho ,  Ming-Han Lee

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US09343356B2

公开(公告)日：2016-05-17

申请号：US13771175

申请日：2013-02-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chi-Liang Kuo ,  Tz-Jun Kuo ,  Hsiang-Huan Lee

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76832 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

摘要翻译： 本公开涉及一种形成后端金属互连层的方法。 该方法通过在半导体衬底上沉积一个或多个自组装单层来限定金属互连层区域来进行。 在金属互连层区域内的半导体衬底上形成具有多个金属结构的金属互连层。 然后在多个金属结构之间的区域中在半导体衬底的表面上形成层间电介质层。

公开(公告)号：US10453740B2

公开(公告)日：2019-10-22

申请号：US15679385

申请日：2017-08-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tz-Jun Kuo ,  Chien-Hsin Ho ,  Ming-Han Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.