公开(公告)号：US20240274528A1

公开(公告)日：2024-08-15

申请号：US18641745

申请日：2024-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252

Abstract: An interconnect structure includes a via including a first barrier layer and a bulk layer disposed over the first barrier layer, and a conductive line disposed over a top surface of the via. The conductive line includes a conductive layer disposed over a top surface of the bulk layer, and a second barrier layer disposed on sidewalls of the conductive layer. The interconnect structure is free of a nitride layer between the bulk layer and the conductive layer.

公开(公告)号：US20190096806A1

公开(公告)日：2019-03-28

申请号：US16200076

申请日：2018-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A structure includes a non-insulator structure, an etch stop layer, a dielectric layer, a conductive feature, and a first diffusion barrier layer. The etch stop layer is over the non-insulator structure. The dielectric layer is over the etch stop layer. The conductive feature is in the dielectric layer. The first diffusion barrier layer wraps around the conductive feature, the first diffusion barrier layer has a base portion between the non-insulator structure and the conductive feature, and the first diffusion barrier layer has a lateral extension from the base portion of the first diffusion barrier layer.

公开(公告)号：US20180350741A1

公开(公告)日：2018-12-06

申请号：US16048921

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/8234

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

公开(公告)号：US20180166333A1

公开(公告)日：2018-06-14

申请号：US15675498

申请日：2017-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76879 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1036

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.

公开(公告)号：US20170092591A1

公开(公告)日：2017-03-30

申请号：US15361699

申请日：2016-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Kang FU ,  Hsien-Chang WU ,  Li-Lin SU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

公开(公告)号：US20200091055A1

公开(公告)日：2020-03-19

申请号：US16135088

申请日：2018-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/498 ,  H01L23/532 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive feature over a substrate. The method also includes forming an insulating layer over the substrate and covering the first conductive feature. The method also includes forming a first opening in the insulating layer to expose the first conductive feature. The method also includes recessing the exposed first conductive feature through the first opening, so as to form a second opening in the first conductive feature and below the first opening. The method also includes filling the first opening and the second opening with a second conductive feature.

公开(公告)号：US20190006230A1

公开(公告)日：2019-01-03

申请号：US15679385

申请日：2017-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Jun KUO ,  Chien-Hsin HO ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329

Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US20180350913A1

公开(公告)日：2018-12-06

申请号：US15675535

申请日：2017-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ching-Fu YEH ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L29/16 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L29/1606 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US20170287842A1

公开(公告)日：2017-10-05

申请号：US15632184

申请日：2017-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Kang FU ,  Hsien-Chang WU ,  Li-Lin SU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

公开(公告)号：US20170229372A1

公开(公告)日：2017-08-10

申请号：US15016886

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/3736 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the dielectric layer, and the conductive feature includes a catalyst layer and a conductive element. The catalyst layer is between the conductive element and the dielectric layer, and the catalyst layer is in physical contact with the conductive element. The catalyst layer continuously surrounds a sidewall and a bottom of the conductive element. The catalyst layer is made of a material different from that of the conductive element, and the catalyst layer is capable of lowering a formation temperature of the conductive element.