公开(公告)号：US20190006230A1

公开(公告)日：2019-01-03

申请号：US15679385

申请日：2017-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Jun KUO ,  Chien-Hsin HO ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329

Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US20220262675A1

公开(公告)日：2022-08-18

申请号：US17734683

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Jun Kuo ,  Chien-Hsin HO ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US20200035546A1

公开(公告)日：2020-01-30

申请号：US16593562

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tz-Jun KUO ,  Chien-Hsin HO ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.