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    Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability
    5.
    发明授权
    Two 2D capping layers on interconnect conductive structure to increase interconnect structure reliability 有权

    公开(公告)号：US11532549B2

    公开(公告)日：2022-12-20

    申请号：US17097406

    申请日：2020-11-13

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shu-Wei Li ,  Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768

    摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. A first interconnect conductive structure extends through the first interconnect dielectric layer. A first capping layer is arranged over the first interconnect conductive structure, and a second capping layer is arranged over the first capping layer. The first capping layer includes a first two-dimensional material that is different than a second two-dimensional material of the second capping layer. An etch stop layer is arranged over the first interconnect dielectric layer and the second capping layer. The integrated chip further includes a second interconnect dielectric layer arranged over the etch stop layer and a second interconnect conductive structure extending through the second interconnect dielectric layer and the etch stop layer to contact the first interconnect conductive structure.

    INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAP
    6.
    发明申请
    INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAP 有权

    公开(公告)号：US20220310446A1

    公开(公告)日：2022-09-29

    申请号：US17213888

    申请日：2021-03-26

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chin-Lung Chung ,  Shin-Yi Yang ,  Ming-Han Lee

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    摘要： A method includes providing a substrate, a dielectric layer over the substrate, and metallic features over the dielectric layer; and forming an organic blocking layer (OBL) over the dielectric layer and between lower portions of the metallic features. The OBL covers sidewall surfaces of the lower portions, but not upper portions, of the metallic features. The method further includes depositing a dielectric barrier layer over top surfaces of the metallic features and over the sidewall surfaces of the upper portions of the metallic features, wherein at least a portion of a top surface of the OBL is not covered by the dielectric barrier layer; forming an inter-metal dielectric (IMD) layer between the metallic features and above the OBL; and removing the OBL, leaving an air gap above the dielectric layer, below the dielectric barrier layer and the IMD layer, and laterally between the lower portions of the metallic features.

    Chemical mechanical polishing topography reset and control on interconnect metal lines
    7.
    发明授权
    Chemical mechanical polishing topography reset and control on interconnect metal lines 有权

    公开(公告)号：US11342219B2

    公开(公告)日：2022-05-24

    申请号：US17033270

    申请日：2020-09-25

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shih-Kang Fu ,  Ming-Han Lee

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    摘要： A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.

    Method with CMP for metal ion prevention
    8.
    发明授权
    Method with CMP for metal ion prevention 有权

    公开(公告)号：US11211256B2

    公开(公告)日：2021-12-28

    申请号：US16801526

    申请日：2020-02-26

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/67 ,  C09G1/02 ,  H01L21/3213

    摘要： The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

    Methods of performing chemical-mechanical polishing process in semiconductor devices
    9.
    发明授权
    Methods of performing chemical-mechanical polishing process in semiconductor devices 有权

    公开(公告)号：US11152255B2

    公开(公告)日：2021-10-19

    申请号：US16712430

    申请日：2019-12-12

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

    摘要： A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.