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    SELECTIVE CONTACT ETCH FOR UNMERGED EPITAXIAL SOURCE/DRAIN REGIONS
    71.
    发明申请
    SELECTIVE CONTACT ETCH FOR UNMERGED EPITAXIAL SOURCE/DRAIN REGIONS 审中-公开
    选择性接触蚀刻用于未经浇灌的外来源/排水区

    公开(公告)号：US20170047325A1

    公开(公告)日：2017-02-16

    申请号：US14826956

    申请日：2015-08-14

    Applicant: International Business Machines Corporation

    Inventor： Sanjay C. Mehta ,  Alexander Reznicek

    IPC: H01L27/088 ,  H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/08 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/04

    CPC classification number: H01L27/0886 ,  H01L21/02167 ,  H01L21/283 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.

    Abstract translation: 半导体结构包括位于基板表面上的多个半导体材料翅片。 至少一个栅极结构跨越每个半导体材料鳍片的一部分。 未熔化的源极侧外延半导体材料部分位于每个半导体材料鳍的暴露表面上，并且在每个栅极结构的一侧上，并且未熔接的漏极侧外延半导体部分位于每个半导体材料鳍的其它暴露表面上，并且在另一侧 的每个门结构。 蚀刻停止结构位于每个未掺杂的源极侧和外侧半导体材料部分之间。 每个蚀刻停止结构包括与蚀刻停止结构的上部材料部分相比在特定蚀刻剂中具有更高的耐蚀刻性的底部材料部分。

    Replacement metal gate finFET
    73.
    发明授权
    Replacement metal gate finFET 有权
    替代金属栅极finFET

    公开(公告)号：US09530651B2

    公开(公告)日：2016-12-27

    申请号：US14609790

    申请日：2015-01-30

    Applicant: International Business Machines Corporation

    Inventor： Hemanth Jagannathan ,  Sanjay C. Mehta ,  Junli Wang ,  Chun-Chen Yeh ,  Stefan Schmitz

    IPC: H01L27/12 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L21/28132 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

    Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

    Abstract translation: 场效应晶体管器件包括鳍状物，其包括布置在绝缘体层上的半导体材料，鳍包括沟道区，部分地布置在鳍的沟道区上的硬掩模层，布置在硬掩模层上并在沟道上方的栅叠层 翅片的区域，布置在硬掩模层的第一部分上的金属合金层，邻近栅极堆叠布置的金属合金层，以及邻近栅极堆叠并在金属合金层上方布置的第一间隔物。

    Replacement metal gate FinFET
    74.
    发明授权
    Replacement metal gate FinFET 有权

    公开(公告)号：US09472407B2

    公开(公告)日：2016-10-18

    申请号：US14609690

    申请日：2015-01-30

    Applicant: International Business Machines Corporation

    Inventor： Hemanth Jagannathan ,  Sanjay C. Mehta ,  Junli Wang ,  Chun-Chen Yeh ,  Stefan Schmitz

    IPC: H01L27/12 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L21/28132 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

    Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.

    Field effect transistor device spacers
    75.
    发明授权
    Field effect transistor device spacers 有权
    场效应晶体管器件间隔物

    公开(公告)号：US09425292B1

    公开(公告)日：2016-08-23

    申请号：US15085112

    申请日：2016-03-30

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

    IPC: H01L29/66 ,  H01L21/00

    CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

    Abstract translation: 一种用于制造场效应晶体管器件的方法，包括在衬底上形成翅片，在鳍片上形成第一虚拟栅极堆叠和第二虚拟栅极堆叠，形成与鳍片相邻的间隔物，第一伪栅极堆叠和第二虚拟栅极 栅极堆叠，蚀刻以去除所述鳍片的部分并形成由所述间隔物部分地限定的第一空腔，在所述第一腔体中沉积绝缘体材料，在第一虚拟栅极堆叠和所述鳍片的部分上图案化掩模，蚀刻以去除暴露部分 并且在所述鳍的暴露部分上外延生长第一半导体材料。

    Spacer replacement for replacement metal gate semiconductor devices
    78.
    发明授权
    Spacer replacement for replacement metal gate semiconductor devices 有权
    替代金属栅极半导体器件的间隔件替代

    公开(公告)号：US09171927B2

    公开(公告)日：2015-10-27

    申请号：US13850470

    申请日：2013-03-26

    Applicant: International Business Machines Corporation

    Inventor： Sanjay C. Mehta ,  Shom S. Ponoth ,  Muthumanickam Sankarapandian ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC: H01L21/336 ,  H01L21/311 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

    CPC classification number: H01L29/66553 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

    Abstract translation: 一种方法，包括从具有牺牲栅极的半导体器件去除包括硬掩模层和一个或多个间隔物材料层的第一介电材料的步骤，所述牺牲栅极的侧壁被所述间隔物材料层覆盖，以及升高的源极和升高的漏极 其中所述牺牲栅极与所述牺牲栅极一起被所述硬掩模层覆盖，其中所述去除对所述牺牲栅极，升高的源极区域和升高的漏极区域是选择性的，并且在每个所述升高的源极区域，升高的漏极区域 和牺牲门。 该方法包括将第二介电材料的共形层沉积到半导体器件中，其中第二材料在均匀的层中符合升高的源极区域，升高的漏极区域和牺牲栅极，并且填充每个凸起源极区域之间的空隙 ，凸起的漏极区域和牺牲栅极。

    SPACER REPLACEMENT FOR REPLACEMENT METAL GATE SEMICONDUCTOR DEVICES
    79.
    发明申请
    SPACER REPLACEMENT FOR REPLACEMENT METAL GATE SEMICONDUCTOR DEVICES 有权
    替代金属栅极半导体器件的间隔替换

    公开(公告)号：US20140295637A1

    公开(公告)日：2014-10-02

    申请号：US13850470

    申请日：2013-03-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Sanjay C. Mehta ,  Shom S. Ponoth ,  Muthumanickam Sankarapandian ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC: H01L21/311 ,  H01L21/02 ,  H01L29/66

    CPC classification number: H01L29/66553 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

    Abstract translation: 一种方法，包括从具有牺牲栅极的半导体器件去除包括硬掩模层和一个或多个间隔物材料层的第一介电材料的步骤，所述牺牲栅极的侧壁被所述间隔物材料层覆盖，以及升高的源极和升高的漏极 其中所述牺牲栅极与所述牺牲栅极一起被所述硬掩模层覆盖，其中所述去除对所述牺牲栅极，升高的源极区域和升高的漏极区域是选择性的，并且在每个所述升高的源极区域，升高的漏极区域 和牺牲门。 该方法包括将第二介电材料的共形层沉积到半导体器件中，其中第二材料在均匀的层中符合升高的源极区域，升高的漏极区域和牺牲栅极，并且填充每个凸起源极区域之间的空隙 ，凸起的漏极区域和牺牲栅极。

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