公开(公告)号：US09634028B2

公开(公告)日：2017-04-25

申请号：US14929307

申请日：2015-10-31

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L29/00 ,  H01L27/12 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L29/06 ,  H01L21/283

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/845 ,  H01L23/485 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance.Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

公开(公告)号：US20170092765A1

公开(公告)日：2017-03-30

申请号：US14871042

申请日：2015-09-30

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pouya Hashemi ,  Alexander Reznicek ,  Joshua M. Rubin ,  Robin M. Schulz

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02318 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823418 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.

公开(公告)号：US20160343734A1

公开(公告)日：2016-11-24

申请号：US14718500

申请日：2015-05-21

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/845 ,  H01L23/485 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

Abstract translation: 提供FinFET器件，其中电流路径被最小化，并且在通道载体到达金属触点之前主要限于间隔区域。 源极/漏极区域中的鳍片被金属化以增加接触面积并降低接触电阻。 源极/漏极外延后的源极/漏极区域中选择性去除半导体鳍片有助于金属化鳍片的更换。 在源极/漏极外延之后形成的间隔物在半导体鳍片去除期间防止了延伸/沟道区域的蚀刻。

公开(公告)号：US09472621B1

公开(公告)日：2016-10-18

申请号：US14955738

申请日：2015-12-01

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Joshua M. Rubin

IPC: H01L21/84 ,  H01L31/18 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/02614 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32105 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins includes performing a first, partial fin etch on a tensile strained silicon layer of a semiconductor substrate; selectively oxidizing bottom surfaces of the tensile strained silicon layer in a PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and performing a second fin etch to define NFET silicon fins in an NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.

Abstract translation: 一种形成具有选择性拉伸应变NFET鳍片和弛豫PFET鳍片的CMOS结构的方法包括在半导体衬底的拉伸应变硅层上执行第一部分鳍片蚀刻; 选择性地氧化半导体衬底的PFET区域中的拉伸应变硅层的底表面，从而使在PFET区域中限定的PFET硅翅片变得松弛; 以及执行第二鳍蚀刻以在所述半导体衬底的NFET区域中限定NFET硅散热片，其中所述NFET硅散热片保持拉伸应变。

公开(公告)号：US20250031448A1

公开(公告)日：2025-01-23

申请号：US18357085

申请日：2023-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Nicholas Alexander Polomoff ,  Joshua M. Rubin

IPC: H01L27/12

Abstract: A semiconductor device includes source and drain regions above a substrate layer and a dielectric bar between each of the source and drain regions. Each of the source and drain regions has a filleted shape, with a bottom portion of the filleted shape including a horizontal bottom surface connecting two sloped surfaces. Two sloped surfaces on a backside of the semiconductor device are surrounded by a metal contact.

公开(公告)号：US20250006780A1

公开(公告)日：2025-01-02

申请号：US18346125

申请日：2023-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin ,  Alexander Reznicek ,  Theodorus E. Standaert ,  Koichi Motoyama

IPC: H01L21/02 ,  H01G4/012 ,  H01G4/33 ,  H01G4/008

Abstract: A pillar or trench structure in a substrate includes vertical portions and one or more indented cavities in a sidewall between the vertical portions. The indented cavities are partial undercuts substantially traverse to the vertical portions pillar structure, or separate undercuts attached to an anchor. A higher capacitance density is achieved through the layering of multiple conductive contact layers and insulating layers in the undercuts and the vertical portions of the pillar or trench structure.

公开(公告)号：US11855191B2

公开(公告)日：2023-12-26

申请号：US17450121

申请日：2021-10-06

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Junli Wang ,  Indira Seshadri ,  Chen Zhang ,  Ruilong Xie ,  Joshua M. Rubin ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/66803 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/7855

Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

公开(公告)号：US11756957B2

公开(公告)日：2023-09-12

申请号：US17321563

申请日：2021-05-17

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Tenko Yamashita ,  Joshua M. Rubin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

公开(公告)号：US20230197705A1

公开(公告)日：2023-06-22

申请号：US17552754

申请日：2021-12-16

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Steven Lorenz Wright ,  Arvind Kumar ,  Mounir Meghelli

IPC: H01L25/18

CPC classification number: H01L25/18

Abstract: Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

公开(公告)号：US11587896B2

公开(公告)日：2023-02-21

申请号：US17115882

申请日：2020-12-09

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Yang Liu ,  Steven Lorenz Wright ,  Paul S. Andry

IPC: H01L23/00 ,  H01L23/538

Abstract: A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.