公开(公告)号：US20240429178A1

公开(公告)日：2024-12-26

申请号：US18211669

申请日：2023-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Alexander Polomoff ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Matthew Stephen Angyal ,  Fee Li Lie ,  Ruilong Xie ,  Terence Hook

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/58

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a back end of the line (BEOL) stack including a dielectric stack, and an active device region in the dielectric stack, the active device region including at least one component selected from the group consisting of transistors, capacitors and nanosheet structures; and a crack stop that extends vertically through the active device region.

公开(公告)号：US20250031448A1

公开(公告)日：2025-01-23

申请号：US18357085

申请日：2023-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Nicholas Alexander Polomoff ,  Joshua M. Rubin

IPC: H01L27/12

Abstract: A semiconductor device includes source and drain regions above a substrate layer and a dielectric bar between each of the source and drain regions. Each of the source and drain regions has a filleted shape, with a bottom portion of the filleted shape including a horizontal bottom surface connecting two sloped surfaces. Two sloped surfaces on a backside of the semiconductor device are surrounded by a metal contact.

公开(公告)号：US20250006658A1

公开(公告)日：2025-01-02

申请号：US18216328

申请日：2023-06-29

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander Polomoff ,  Yann Mignot ,  Brent A. Anderson ,  Lawrence A. Clevenger

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A structure comprising: metal lines and viabars that surround a periphery of an active area of a semiconductor device; at least one viabar that extends through multiple layers of the semiconductor device, wherein the at least one viabar connects a metal line of one layer of the structure with a metal line of another layer of the structure; and a connection viabar that terminates at a metal line of a layer between the one layer of the structure and the another layer of the structure, wherein a thickness of the connection viabar is less than a thickness of the at least one viabar.

公开(公告)号：US20240113055A1

公开(公告)日：2024-04-04

申请号：US17937429

申请日：2022-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Alexander Polomoff ,  Eric Perfecto ,  Katsuyuki Sakuma ,  Mukta Ghate Farooq ,  Spyridon Skordas ,  Sathyanarayanan Raghavan ,  Michael P. Belyansky

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03019 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06593 ,  H01L2924/3512

Abstract: A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.

公开(公告)号：US20240105612A1

公开(公告)日：2024-03-28

申请号：US17954514

申请日：2022-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Nicholas Alexander Polomoff ,  Brent A. Anderson ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L29/417

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/41725

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

公开(公告)号：US20250048677A1

公开(公告)日：2025-02-06

申请号：US18363889

申请日：2023-08-02

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Ruilong Xie ,  Tsung-Sheng Kang ,  Nicholas Alexander Polomoff ,  Huimei Zhou

IPC: H01L29/423 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes first nanosheet structures at an NFET region of a semiconductor substrate and second nanosheet structures at a PFET region. A first gate wraps around the first nanosheet structures and a second gate wraps around the second plurality of nanosheet structures. A dielectric bar is between the first nanosheet structures and the second nanosheet structures. The semiconductor device further includes a first backside contact in the NFET region and a second backside contact in the PFET region. The first backside contact includes a first backside contact extension that extends to a first side of the at least one dielectric bar. The second backside contact includes a second backside contact extension that extends to an opposing second side of the at least one dielectric bar. One or more backside power elements are on one or both of the first backside contact extension and the second contact extension.

公开(公告)号：US20240332239A1

公开(公告)日：2024-10-03

申请号：US18191950

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Nicholas Alexander Polomoff ,  Mukta Ghate Farooq ,  Dale Curtis McHerron ,  Eric Perfecto ,  Katsuyuki Sakuma ,  SPYRIDON SKORDAS

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/80357 ,  H01L2224/95

Abstract: A three-dimensional (3D) die architecture is provided. The 3D die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.

公开(公告)号：US20240105613A1

公开(公告)日：2024-03-28

申请号：US17954826

申请日：2022-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Kisik Choi ,  Son Nguyen ,  Nicholas Alexander Polomoff

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device includes a frontside including first metal structures, transistors disposed between the frontside and a backside opposite the frontside, each transistor including a source/drain positioned within a stack of nanolayers, the stack of nanolayers forming a gate structure and a power circuit on the backside and connected to the transistors by backside contacts. A backside dielectric isolation has a horizontal portion along a backside of the gate structure and a vertical portion substantially perpendicular to the backside and self-aligned to selected source/drains to electrically isolate the power circuit from the transistors.