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    Semiconductor device and method for producing a semiconductor device
    61.
    发明授权
    Semiconductor device and method for producing a semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US09553130B2

    公开(公告)日：2017-01-24

    申请号：US15093986

    申请日：2016-04-08

    Applicant: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

    Inventor： Fujio Masuoka ,  Hiroki Nakamura

    IPC: H01L29/76 ,  H01L31/062 ,  H01L27/22 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L43/12 ,  H01L21/0273 ,  H01L21/32055 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/768 ,  H01L23/528 ,  H01L27/228 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08

    Abstract: A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film around the semiconductor layer, a first gate line around the first gate insulating film, a third gate insulating film around an upper portion of the semiconductor layer, a first contact electrode around the third gate insulating film, a second contact electrode connecting upper portions of the semiconductor layer and the first contact electrode, and a magnetic tunnel junction storage element on the second contact electrode, a first source line connecting lower portions of the semiconductor layers to each other, a first bit line extending in a direction perpendicular to a direction of the first gate line and connected to an upper portion of the storage element, and a second source line extending in a direction perpendicular to the first source line.

    Abstract translation: 半导体器件包括布置在一行上的四个或更多个存储单元，每个存储单元包括第一柱状半导体层，围绕半导体层的第一栅极绝缘膜，围绕第一栅极绝缘膜的第一栅极线，第三栅极绝缘膜 围绕半导体层的上部的栅极绝缘膜，围绕第三栅极绝缘膜的第一接触电极，连接半导体层的上部和第一接触电极的第二接触电极和第二接触电极的第二接触电极 接触电极，将半导体层的下部彼此连接的第一源极线，沿与第一栅极线的方向垂直的方向延伸并连接到存储元件的上部的第一位线，以及第二源极 线在垂直于第一源极线的方向上延伸。

    FinFET device and fabrication method thereof
    62.
    发明授权
    FinFET device and fabrication method thereof 有权
    FinFET器件及其制造方法

    公开(公告)号：US09514994B2

    公开(公告)日：2016-12-06

    申请号：US14987192

    申请日：2016-01-04

    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

    Inventor： Jianhua Ju

    IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/148 ,  H01L29/768 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0924

    Abstract: A method for forming a FinFET device is provided. The method includes providing a substrate having a first region and a second region; and forming a plurality of fins on the substrate. The method also includes forming a plurality of doping regions with different doping concentrations in the fins in the first region; and forming a plurality of dummy gate structures over the plurality of fins. Further, the method includes forming source and drain regions in the plurality of fins at both sides of the dummy gate structures; and removing the dummy gate structures to form a plurality of openings to expose the plurality of fins. Further, the method also includes forming a plurality of work function layers with different work functions on the exposed fins in the openings in the second region; and forming gate structures in the openings.

    Abstract translation: 提供了一种形成FinFET器件的方法。 该方法包括提供具有第一区域和第二区域的衬底; 并在基板上形成多个翅片。 该方法还包括在第一区域的翅片中形成具有不同掺杂浓度的多个掺杂区域; 以及在所述多个翅片上形成多个虚拟栅极结构。 此外，该方法包括在虚拟栅极结构的两侧的多个鳍中形成源区和漏区; 以及去除所述虚拟栅极结构以形成多个开口以暴露所述多个翅片。 此外，该方法还包括在第二区域的开口中的暴露的翅片上形成具有不同功函数的多个功函数层; 以及在开口中形成门结构。

    Multi-composition gate dielectric field effect transistors
    65.
    发明授权
    Multi-composition gate dielectric field effect transistors 有权
    多组合栅介质场效应晶体管

    公开(公告)号：US09397175B2

    公开(公告)日：2016-07-19

    申请号：US14881766

    申请日：2015-10-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/40 ,  H01L29/51 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

    CPC classification number: H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

    Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

    Abstract translation: 在半导体材料层上形成第一栅极结构和第二栅极结构。 第一栅极结构包括平面硅基栅极电介质，平面高k栅极电介质，金属氮化物部分和第一半导体材料部分，并且第二栅极结构包括硅基电介质材料部分和第二半导体 材料部分。 在形成栅极间隔物和平坦化介电层之后，用包括化学氧化物部分和第二高k栅极电介质的瞬态栅极结构来代替第二栅极结构。 可以通过更换半导体材料部分在每个栅电极中形成功函数金属层和导电材料部分。 栅电极包括平面硅基栅极电介质，平面高k栅极电介质和U形高k栅极电介质，另一个栅电极包括化学氧化物部分和另一个U形高k栅极电介质 。

    CMOS image sensor
    66.
    发明授权
    CMOS image sensor 有权
    CMOS图像传感器

    公开(公告)号：US09390929B2

    公开(公告)日：2016-07-12

    申请号：US14246827

    申请日：2014-04-07

    Applicant: Intellectual Ventures II LLC

    Inventor： Won-Ho Lee

    IPC: H01L31/062 ,  H01L31/113 ,  H01L21/28 ,  H01L27/146 ,  H04N5/365 ,  H01L29/423

    CPC classification number: H01L27/14614 ,  H01L21/28008 ,  H01L27/14603 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/42372 ,  H04N5/3658 ,  H04N5/374

    Abstract: A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.

    Abstract translation: CMOS图像传感器包括光电二极管，用于将在光电二极管处累积的电荷传送到一列列的多个晶体管，以及连接到多个晶体管中的至少一个晶体管的栅电极的降压元件，用于扩展 晶体管通过降低输入至少一个晶体管的栅电极的栅极电压。

    High-voltage field-effect transistor and method of making the same
    67.
    发明授权
    High-voltage field-effect transistor and method of making the same 有权
    高压场效应晶体管及其制作方法

    公开(公告)号：US09362395B2

    公开(公告)日：2016-06-07

    申请号：US14385487

    申请日：2013-01-25

    Applicant: ams AG

    Inventor： Martin Knaipp

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L29/10

    CPC classification number: H01L29/66659 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

    Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

    Abstract translation: 高电压晶体管器件包括具有第一导电类型的源极区域（2）的半导体衬底（1），体区域（3），其包括与第二导电相反的第二导电类型的沟道区域（4） 第一导电类型的第一类型，第一导电类型的漂移区域（5）和从沟道区域（4）到漏极区域（6）纵向延伸的第一类型导电体的漏极区域（6） ）并由隔离区域（9）侧向限制。 漂移区域（5）包括掺杂第一类型的导电性并且包括具有第二类型导电性的净掺杂的附加区域（8），以调整漂移区域（5）的电性能。 漂移区域深度和附加区域深度不超过隔离区域（9）的最大深度（17）。

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