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    Techniques for fabricating Janus sensors
    2.
    发明授权
    Techniques for fabricating Janus sensors 有权
    制造Janus传感器的技术

    公开(公告)号：US09251978B2

    公开(公告)日：2016-02-02

    申请号：US13875394

    申请日：2013-05-02

    申请人： GLOBALFOUNDRIES INC.

    发明人： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

    IPC分类号： G01N27/404 ,  H01H29/02 ,  G01N33/00 ,  G01N15/10 ,  G01N27/327 ,  G01N27/447

    CPC分类号： H01H29/02 ,  G01N15/1031 ,  G01N27/3278 ,  G01N27/404 ,  G01N27/44795 ,  G01N33/0009 ,  Y10T29/49117

    摘要： Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid.

    摘要翻译： 提供采用Janus微/纳米组件的机电传感器及其制造技术。 一方面，制造机电传感器的方法包括以下步骤。 在基板上形成背栅。 栅极电介质沉积在背栅上。 在背栅上形成中间层，其中形成有微流体通道。 顶部电极形成在微流体通道上方。 一个或多个Janus部件被放置在微流体通道中，其中Janus部件中的每一个具有具有导电材料的第一部分和具有电绝缘材料的第二部分。 微流体通道充满流体。 电绝缘材料在流体的pH下具有负的表面电荷，并且在pH小于流体的pH的pH下具有等电点。

    METAL SEMICONDUCTOR ALLOY CONTACT WITH LOW RESISTANCE
    3.
    发明申请
    METAL SEMICONDUCTOR ALLOY CONTACT WITH LOW RESISTANCE 有权
    金属半导体合金与低电阻接触

    公开(公告)号：US20140017862A1

    公开(公告)日：2014-01-16

    申请号：US14028957

    申请日：2013-09-17

    申请人： Globalfoundries Inc. ,  International Business Machines Corporation

    发明人： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

    摘要翻译： 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

    Techniques for fabricating Janus sensors
    5.
    发明授权
    Techniques for fabricating Janus sensors 有权

    公开(公告)号：US09251979B2

    公开(公告)日：2016-02-02

    申请号：US14010945

    申请日：2013-08-27

    申请人： GLOBALFOUNDRIES INC.

    发明人： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

    IPC分类号： G01N27/404 ,  H01H29/02 ,  G01N33/00 ,  G01N15/10 ,  G01N27/327 ,  G01N27/447

    CPC分类号： H01H29/02 ,  G01N15/1031 ,  G01N27/3278 ,  G01N27/404 ,  G01N27/44795 ,  G01N33/0009 ,  Y10T29/49117

    摘要： Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid.

    Multi-composition gate dielectric field effect transistors
    6.
    发明授权
    Multi-composition gate dielectric field effect transistors 有权
    多组合栅介质场效应晶体管

    公开(公告)号：US09397175B2

    公开(公告)日：2016-07-19

    申请号：US14881766

    申请日：2015-10-13

    申请人： GLOBALFOUNDRIES INC.

    发明人： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/40 ,  H01L29/51 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

    CPC分类号： H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

    摘要： A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

    摘要翻译： 在半导体材料层上形成第一栅极结构和第二栅极结构。 第一栅极结构包括平面硅基栅极电介质，平面高k栅极电介质，金属氮化物部分和第一半导体材料部分，并且第二栅极结构包括硅基电介质材料部分和第二半导体 材料部分。 在形成栅极间隔物和平坦化介电层之后，用包括化学氧化物部分和第二高k栅极电介质的瞬态栅极结构来代替第二栅极结构。 可以通过更换半导体材料部分在每个栅电极中形成功函数金属层和导电材料部分。 栅电极包括平面硅基栅极电介质，平面高k栅极电介质和U形高k栅极电介质，另一个栅电极包括化学氧化物部分和另一个U形高k栅极电介质 。