公开(公告)号：US20140017862A1

公开(公告)日：2014-01-16

申请号：US14028957

申请日：2013-09-17

申请人： Globalfoundries Inc. ,  International Business Machines Corporation

发明人： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

摘要翻译： 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

公开(公告)号：US08987078B2

公开(公告)日：2015-03-24

申请号：US14028957

申请日：2013-09-17

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

发明人： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

摘要翻译： 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

公开(公告)号：US20160343664A1

公开(公告)日：2016-11-24

申请号：US15228170

申请日：2016-08-04

申请人： International Business Machines Corporation

发明人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L23/535 ,  H01L29/10 ,  H01L29/78 ,  H01L29/45

CPC分类号： H01L29/7833 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/45 ,  H01L29/456 ,  H01L29/458 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

公开(公告)号：US09455195B2

公开(公告)日：2016-09-27

申请号：US14561550

申请日：2014-12-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Paul Chang ,  Katsunori Onishi ,  Jian Yu

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8238

CPC分类号： H01L29/41783 ,  H01L21/02362 ,  H01L21/3081 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

摘要： A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.

摘要翻译： 公开了一种性能优化的CMOS FET结构和制造方法。 该方法包括形成用于第一类型器件和第二类型器件的源极和漏极区域。 该方法还包括降低第一类型器件的源极和漏极区域，同时保护用于第二类型器件的源极和漏极区域。 该方法还包括执行硅化物工艺以在用于第一类型器件的降低的源极和漏极区域以及用于第二类型器件的源极和漏极区域上形成硅化物区域。

公开(公告)号：US09425309B2

公开(公告)日：2016-08-23

申请号：US14483923

申请日：2014-09-11

申请人： International Business Machines Corporation

发明人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/45 ,  H01L29/456 ,  H01L29/458 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

摘要翻译： 提供一种半导体器件，其包括在衬底的沟道区上的栅极结构。 源极区域和漏极区域存在于沟道区域的相对侧上。 第一金属半导体合金存在于源区和漏区中的至少一个的上表面上。 第一金属半导体合金延伸到栅极结构的侧壁。 介电层存在于栅极结构和第一金属半导体合金之上。 存在通过电介质层到与栅极结构分离的第一金属半导体合金的一部分的开口。 第二金属半导体合金存在于开口中，与第一金属半导体合金直接接触，并且具有垂直偏移的上表面并且位于第一金属半导体合金的上表面之上。

公开(公告)号：US20150137269A1

公开(公告)日：2015-05-21

申请号：US14571628

申请日：2014-12-16

申请人： International Business Machines Corporation

发明人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC分类号： H01L29/423

CPC分类号： H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

摘要翻译： 在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。 去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。 栅组件可以用作栅极电介质或功函数金属部分，以形成增强替代栅极场效应晶体管的性能的栅极结构。

公开(公告)号：US08969933B2

公开(公告)日：2015-03-03

申请号：US13780877

申请日：2013-02-28

申请人： International Business Machines Corporation

发明人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

摘要翻译： 在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。 去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。 栅组件可以用作栅极电介质或功函数金属部分，以形成增强替代栅极场效应晶体管的性能的栅极结构。

公开(公告)号：US09735268B2

公开(公告)日：2017-08-15

申请号：US15228170

申请日：2016-08-04

申请人： International Business Machines Corporation

发明人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/535 ,  H01L29/10

CPC分类号： H01L29/7833 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/45 ,  H01L29/456 ,  H01L29/458 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

公开(公告)号：US20150318371A1

公开(公告)日：2015-11-05

申请号：US14797982

申请日：2015-07-13

申请人： International Business Machines Corporation

发明人： Nicolas Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg ,  Jian Yu

IPC分类号： H01L29/45 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/456 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

摘要： Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.

公开(公告)号：US09153546B2

公开(公告)日：2015-10-06

申请号：US14454041

申请日：2014-08-07

申请人： International Business Machines Corporation

发明人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L21/332 ,  H01L23/52 ,  H01L23/62 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  G11C17/16 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L23/62 ,  G11C17/16 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/84 ,  H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.

摘要翻译： 电熔丝在半导体衬底的表面上具有阳极接触。 电熔丝在半导体衬底的与阳极接触件间隔开的表面上具有阴极接触。 电熔丝在衬底内具有连接阳极接触件和阴极接触件的连接。 该连接件包括半导体层和硅化物层。 硅化物层延伸超过阳极接触。 硅化物层的另一端延伸超过阴极接触。 在硅化物层之下的阳极接触和阴极接触之间的半导体层中嵌入硅锗区。