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    ASYMMETRIC STRESSOR DRAM
    4.
    发明申请
    ASYMMETRIC STRESSOR DRAM 有权
    不对称压力DRAM

    公开(公告)号：US20150349121A1

    公开(公告)日：2015-12-03

    申请号：US14476897

    申请日：2014-09-04

    申请人： International Business Machines Corporation

    发明人： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

    IPC分类号： H01L29/78 ,  H01L27/108

    CPC分类号： H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

    摘要： A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

    摘要翻译： 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平面化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

    Low energy ion implantation of a junction butting region
    5.
    发明授权
    Low energy ion implantation of a junction butting region 有权
    结合对接区域的低能离子注入

    公开(公告)号：US09136321B1

    公开(公告)日：2015-09-15

    申请号：US14265410

    申请日：2014-04-30

    申请人： International Business Machines Corporation

    发明人： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/78 ,  H01L21/36 ,  H01L29/66

    CPC分类号： H01L27/10802 ,  H01L21/84 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/66636 ,  H01L29/78

    摘要： The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

    摘要翻译： 本发明一般涉及半导体器件，更具体地，涉及使用低能离子注入形成结对接区域以减少高密度共享公共接触的相邻FET之间的寄生泄漏和体对体泄漏的结构和方法 存储器技术，例如动态随机存取存储器（DRAM）器件和嵌入式DRAM（eDRAM）器件。 所公开的方法可以包括在使用低能离子注入的半导体绝缘体（SOI）层上形成的沟槽的底部形成接合对接区域，并使用保护层保护相邻结构免受离子散射的损害。

    ASYMMETRIC STRESSOR DRAM
    6.
    发明申请
    ASYMMETRIC STRESSOR DRAM 审中-公开
    不对称压力DRAM

    公开(公告)号：US20150348972A1

    公开(公告)日：2015-12-03

    申请号：US14291094

    申请日：2014-05-30

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10861 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

    摘要： A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. The asymmetric stressor enables low leakage current for the body region during charge storage while the drain voltage is low, and enables a body potential coupled to the drain region and a lower threshold voltage for the access transistor during read and write operations.

    摘要翻译： 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 不对称应力器在漏极电压低时在电荷存储期间使身体区域具有低的漏电流，并且在读取和写入操作期间使能耦合到漏极区域的体电位和用于存取晶体管的较低阈值电压。