公开(公告)号：US06965530B2

公开(公告)日：2005-11-15

申请号：US11029454

申请日：2005-01-06

Applicant: Koji Shimbayashi

Inventor： Koji Shimbayashi

IPC: G11C16/02 ,  G11C7/10 ,  G11C16/06 ,  G11C16/26 ,  G11C7/00

CPC classification number: G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C16/26

Abstract: A semiconductor memory device wherein, in continuous data reading, a notification signal to notify whether a suspend mode is entered or not is given synchronously with data output control according to an output control signal with a suspend function, and a method of controlling the device. When an output enable signal is also used as a suspend instruction, a synchronizing circuit synchronizes the output enable signal with a clock signal to output a synchronized output enable signal. This synchronized output enable signal is supplied to a ready control circuit and an output buffer circuit so that the output control of data and ready signal is performed in synchronization with the clock signal. A data terminal goes into a high impedance state in synchronization with the clock signal, which notifies transition to the suspend mode. This quickly notifies that the system bus has become open.

Abstract translation: 一种半导体存储器件，其中在连续数据读取中，根据具有暂停功能的输出控制信号与数据输出控制同步地给出通知是否进入暂停模式的通知信号，以及控制该器件的方法。 当输出使能信号也用作挂起指令时，同步电路使输出使能信号与时钟信号同步，以输出同步的输出使能信号。 该同步输出使能信号被提供给就绪控制电路和输出缓冲电路，使得与时钟信号同步地执行数据和就绪信号的输出控制。 数据终端与时钟信号同步进入高阻抗状态，通知转换到挂起模式。 这很快就通知系统总线已经开放。

公开(公告)号：US06963501B2

公开(公告)日：2005-11-08

申请号：US10799776

申请日：2004-03-15

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/02 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3454

Abstract: An aspect of the present invention provides a nonvolatile memory that includes a memory cell array including a data storage area to store a data, and a data invert flag storage area to store a data invert flag indicating whether or not the data is inverted. The memory cell array outputs selected data and a data invert flag related to the selected data. A state machine determines whether or not the number of memory cells to which a bias voltage is applied is equal to or greater than a predetermined number when writing data into the memory cell array. The state machine instructs a data controller to transfer inverted data and a data invert flag if it is equal to or greater than the predetermined number.

Abstract translation: 本发明的一个方面提供一种包括存储单元阵列的非易失性存储器，该存储单元阵列包括用于存储数据的数据存储区域和数据反转标志存储区域，以存储指示数据是否反转的数据反转标志。 存储单元阵列输出所选择的数据和与所选数据相关的数据反相标志。 当将数据写入存储单元阵列时，状态机确定施加偏置电压的存储单元的数量是否等于或大于预定数。 如果状态机等于或大于预定数量，则状态机指示数据控制器传送反转数据和数据反转标志。

公开(公告)号：US06963107B2

公开(公告)日：2005-11-08

申请号：US10744797

申请日：2003-12-23

Applicant: Hideto Tomiie ,  Shinji Satoh ,  Kazumasa Nomoto

Inventor： Hideto Tomiie ,  Shinji Satoh ,  Kazumasa Nomoto

IPC: G11C16/02 ,  G11C8/02 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66833 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/7923

Abstract: A nonvolatile semiconductor memory apparatus capable of attaining a low voltage when writing data, wherein charge injection into an unnecessary portion is not performed when reading, and capable of unifying a threshold voltage level when erasing, comprising a first conductive type semiconductor region, two source/drain regions made by a second conductive type semiconductor, a plurality of dielectric films stacked on a first conductive type semiconductor region between the two source/drain regions, and a gate electrode; wherein the first conductive type semiconductor region between the two source/drain regions includes a first region wherein a channel is formed by an inversion layer of a minority carrier and a second region formed between the first region and a source/drain region on one side of the first region and having higher concentration than that of the first region.

公开(公告)号：US20050243602A1

公开(公告)日：2005-11-03

申请号：US11087831

申请日：2005-03-24

Applicant: Akira Umezawa

Inventor： Akira Umezawa

IPC: G11C16/06 ,  G11C11/34 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

Abstract: A semiconductor memory device includes memory cells, a memory cell array, word lines, latch circuits, first row decoders, second row decoders, first isolating transistors, and second isolating transistors. The memory cell includes a memory cell transistor having a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects in common the control gates of the memory cell transistors in a same row. The first row decoder applies a positive voltage to the word lines in a write operation and in an erase operation. The second row decoder applies a negative voltage to the word lines in a write operation and in an erase operation. The first isolating transistor switches between the first row decoder and the word line. The second isolating transistor switches between the second row decoder and the word line.

Abstract translation: 半导体存储器件包括存储单元，存储单元阵列，字线，锁存电路，第一行解码器，第二行解码器，第一隔离晶体管和第二隔离晶体管。 存储单元包括具有浮置栅极和控制栅极的存储单元晶体管。 存储单元阵列包括排列成矩阵的存储单元。 字线公共连接在同一行中的存储单元晶体管的控制栅极。 第一行解码器在写操作和擦除操作中向字线施加正电压。 第二行解码器在写操作和擦除操作中向字线施加负电压。 第一隔离晶体管在第一行解码器和字线之间切换。 第二隔离晶体管在第二行解码器和字线之间切换。

公开(公告)号：US06960805B2

公开(公告)日：2005-11-01

申请号：US10750850

申请日：2004-01-05

Applicant: Byung Jin Ahn ,  Byung Soo Park ,  Sung Jae Chung

Inventor： Byung Jin Ahn ,  Byung Soo Park ,  Sung Jae Chung

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203

Abstract: The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.

Abstract translation: 本发明涉及一种闪存单元及其制造方法，以及闪存单元中的编程/擦除/读取方法。 根据本发明，首先形成源极区域和漏极区域，然后形成隧道氧化膜。 因此，可以防止由于离子注入工艺而引起的隧道氧化膜的损坏。 此外，在浮动栅极下方形成独立的两个沟道区域。 因此，可以在单个单元存储两个或多个位的数据。 此外，隧道氧化物膜，浮栅和具有ONO结构的电介质膜形成在给定的区域。 因此，可以减少处理的步骤并提高装置的电气特性和集成度。

公开(公告)号：US20050237829A1

公开(公告)日：2005-10-27

申请号：US11104599

申请日：2005-04-13

Applicant: Hiroshi Nakamura ,  Tomoharu Tanaka

Inventor： Hiroshi Nakamura ,  Tomoharu Tanaka

IPC: G11C16/06 ,  G11C7/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/30

Abstract: A non-volatile semiconductor memory device comprises a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.

Abstract translation: 非易失性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元 单元格阵列。 在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未选择的字线。 将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二 写入中间电压。

公开(公告)号：US20050237803A1

公开(公告)日：2005-10-27

申请号：US11168331

申请日：2005-06-29

Applicant: Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

Inventor： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

公开(公告)号：US06958934B2

公开(公告)日：2005-10-25

申请号：US10065761

申请日：2002-11-15

Applicant: Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

Inventor： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC: G11C11/56 ,  G11C16/02

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract translation: 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。

公开(公告)号：US20050235118A1

公开(公告)日：2005-10-20

申请号：US10505431

申请日：2003-03-17

Applicant: Katsutoshi Moriyama ,  Hironobu Mori ,  Hisanobu Tsukazaki

Inventor： Katsutoshi Moriyama ,  Hironobu Mori ,  Hisanobu Tsukazaki

IPC: G11C11/14 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C11/15 ,  G11C16/02 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L43/08 ,  G06F13/28

CPC classification number: G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/22 ,  G11C2207/2263

Abstract: It is an object to, in a data storage circuit for storing data, provide a power saving data storage circuit and a data writing method in the data storage circuit, and further, a data storage device. Thus, in the present invention, reading out of existing data stored in a storage element M is performed prior to performing writing of new data to the storage element M to compare the existing data and the new data. The data storage circuit is configured so that in a case where the existing data and the new data are identical with each other, writing to the storage element M is not performed and, in a case where the existing data and the new data are not identical with each other, writing of the new data to the storage element M is performed. The data storage circuit is formed on a semiconductor substrate to have a data storage device.

Abstract translation: 在数据存储电路中存储数据的目的在于，在数据存储电路中提供省电数据存储电路和数据写入方法，另外，还包括数据存储装置。 因此，在本发明中，在对存储元件M进行新数据的写入之前，对存储在存储元件M中的现有数据进行读出，以比较现有数据和新数据。 数据存储电路被配置为使得在现有数据和新数据彼此相同的情况下，不执行对存储元件M的写入，并且在现有数据和新数据不相同的情况下 相互之间，执行将新数据写入存储元件M。 数据存储电路形成在半导体衬底上以具有数据存储装置。

公开(公告)号：US20050232014A1

公开(公告)日：2005-10-20

申请号：US11092969

申请日：2005-03-30

Applicant: Michael Kund ,  Thomas Happ

Inventor： Michael Kund ,  Thomas Happ

IPC: G11C11/34 ,  G11C13/02 ,  G11C16/02 ,  G11C16/34

CPC classification number: G11C13/0011 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069

Abstract: The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by means of an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.

Abstract translation: 本发明涉及一种用于操作存储器单元的系统，存储器组件和用于操作存储单元的过程，其包括活性材料，其可以通过适当的切换过程改变为或多或少的导电状态，由此该过程包括（a ）使存储器单元进入或多或少的导电状态，并且在将存储单元改变为或多或少的导电状态之后评估存储单元的状态。