公开(公告)号：US07072225B2

公开(公告)日：2006-07-04

申请号：US11168331

申请日：2005-06-29

Applicant: Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

Inventor： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

IPC: G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

公开(公告)号：US06999348B2

公开(公告)日：2006-02-14

申请号：US10501391

申请日：2002-02-28

Applicant: Michitaro Kanamitsu ,  Yoshinori Takase ,  Shoji Kubono

Inventor： Michitaro Kanamitsu ,  Yoshinori Takase ,  Shoji Kubono

IPC: G11C11/34

CPC classification number: G11C16/26

Abstract: A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.

Abstract translation: 非易失性半导体存储单元可以通过采用能够减小面积（减少元件数量）的单端感测系统来防止感测锁存电路中的错误检测操作。 提供了使用单端感测系统和NMOS栅极感测系统的闪存芯片。 在单端感测系统中，感测锁存电路连接到全局位线的一端以检测对应于存储器单元的阈值电压的全局位线上的数据。 NMOS栅极感测系统使用NMOSFET在栅极处的全局位线上接收数据，并驱动用于感测锁存电路的节点。 NMOSFET感测感测电压。 感测锁存电路在确保足够的信号量的情况下被激活。 来自施加电源的阈值电压的输出电压预充电全局位线。 以这种方式，可以始终保持NMOSFET的预充电电压和阈值电压之间的恒定差。

公开(公告)号：US06711054B2

公开(公告)日：2004-03-23

申请号：US10298591

申请日：2002-11-19

Applicant: Michitaro Kanamitsu ,  Tetsuya Tsujikawa ,  Toshinori Harada ,  Hiroaki Kotani ,  Shoji Kubono ,  Atsushi Nozoe ,  Takayuki Yoshitake

Inventor： Michitaro Kanamitsu ,  Tetsuya Tsujikawa ,  Toshinori Harada ,  Hiroaki Kotani ,  Shoji Kubono ,  Atsushi Nozoe ,  Takayuki Yoshitake

IPC: G11C1604

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.

Abstract translation: 基于输入到数据锁存电路（DLR和DLL）的附加写入数据和从存储器单元（MC）读取的数据，将写入状态的非易失性存储器单元编程为相同写入状态并编程非易失性存储器 处于擦除状态的单元变成由附加写入数据指示的写入状态。 所生成的数据被锁存在数据锁存电路中以执行用于附加写入的逻辑合成处理。 即使在附加写入操作之后，逻辑合成的数据保留在数据锁存电路中，并且锁存的数据可以被反复用于写入异常。 这样就不需要再次从外部再次接收写入数据。

公开(公告)号：US06459621B1

公开(公告)日：2002-10-01

申请号：US09931030

申请日：2001-08-17

Applicant: Takayuki Kawahara ,  Hiroshi Sato ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Satoshi Noda ,  Shoji Kubono ,  Hiroaki Kotani ,  Katsutaka Kimura

Inventor： Takayuki Kawahara ,  Hiroshi Sato ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Satoshi Noda ,  Shoji Kubono ,  Hiroaki Kotani ,  Katsutaka Kimura

IPC: G11C1134

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract translation: 闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制，直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。 控制涉及第一写入模式（粗写），其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高，并且第二写入 模式（高精度写入），其中阈值电压的变化量相对低。 与高精度模式相比，改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。 因此，使用粗写入模式时的验证操作数量很少，因此可以加快整个写入操作。

公开(公告)号：US06333871B1

公开(公告)日：2001-12-25

申请号：US09539634

申请日：2000-03-30

Applicant: Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

Inventor： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

IPC: G11C1604

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

Abstract translation: 外部提供的程序数据被锁存到数据锁存电路DLL和DLR中。 在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。 与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。 基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。 即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。 即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。

公开(公告)号：US06301150B1

公开(公告)日：2001-10-09

申请号：US09561210

申请日：2000-04-28

Applicant: Michitaro Kanamitsu ,  Tetsuya Tsujikawa ,  Toshinori Harada ,  Hiroaki Kotani ,  Shoji Kubono ,  Atsushi Nozoe ,  Takayuki Yoshitake

Inventor： Michitaro Kanamitsu ,  Tetsuya Tsujikawa ,  Toshinori Harada ,  Hiroaki Kotani ,  Shoji Kubono ,  Atsushi Nozoe ,  Takayuki Yoshitake

IPC: G11C1604

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.

Abstract translation: 基于输入到数据锁存电路（DLR和DLL）的附加写入数据和从存储器单元（MC）读取的数据，将写入状态的非易失性存储器单元编程为相同写入状态并编程非易失性存储器 处于擦除状态的单元变成由附加写入数据指示的写入状态。 所生成的数据被锁存在数据锁存电路中以执行用于附加写入的逻辑合成处理。 即使在附加写入操作之后，逻辑合成的数据保留在数据锁存电路中，并且锁存的数据可以被反复用于写入异常。 这样就不需要再次从外部再次接收写入数据。

公开(公告)号：US5272676A

公开(公告)日：1993-12-21

申请号：US789018

申请日：1991-11-06

Applicant: Shoji Kubono ,  Hiroshi Sato

Inventor： Shoji Kubono ,  Hiroshi Sato

IPC: G11C5/14 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C11/40626 ,  G11C11/406 ,  G11C11/40615 ,  G11C5/145

Abstract: The self-refresh operation of one round of a RAM using dynamic memory cells is accomplished on the basis of the periodic pulses which are formed by an oscillating circuit substantially having no temperature dependency, and the self-refresh period is controlled by a timer circuit using a time constant circuit corresponding to the temperature dependency of the data storage in the memory cells. The operating voltage or boosted output voltage is monitored to switch the circuit operation for generating a plurality kinds of boosted voltages rising sequentially two and three times so that the boosted voltage may be a desired voltage. A control voltage to be fed to the gate of a MOSFET connected between the substrate and the earth potential of the circuit is generated by a dummy substrate voltage generator having a leakage current path varying to follow the fluctuations in a supply voltage.

Abstract translation: 基于由基本上没有温度依赖性的振荡电路形成的周期性脉冲来实现使用动态存储单元的一轮RAM的自刷新操作，并且自刷新周期由定时器电路使用 对应于存储器单元中的数据存储器的温度依赖性的时间常数电路。 监视工作电压或升压输出电压以切换电路操作，以产生依次升高两次和三次的多种升压电压，使得升压电压可以是期望的电压。 通过具有随着电源电压的波动而变化的漏电流路径的虚拟衬底电压发生器产生要馈送到连接在衬底和电路的接地电位之间的MOSFET的栅极的控制电压。

公开(公告)号：US06765840B2

公开(公告)日：2004-07-20

申请号：US10357477

申请日：2003-02-04

Applicant: Hiroshi Sato ,  Shoji Kubono ,  Toshinori Harada ,  Takayuki Kawahara ,  Naoki Miyamoto

Inventor： Hiroshi Sato ,  Shoji Kubono ,  Toshinori Harada ,  Takayuki Kawahara ,  Naoki Miyamoto

IPC: G11C700

CPC classification number: G11C11/5621 ,  G11C7/1048 ,  G11C11/5642 ,  G11C2211/5642

Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Abstract translation: 在通过设定多个阈值将多值信息存储在一个存储单元中的非易失性半导体存储器中，从字线连续读取数据，同时连续地将字线读取电平从最低级别改变到最高级， 并且根据存储在用于存储读取数据的锁存装置中的数据来选择性地预充电下一位线。

公开(公告)号：US06567315B2

公开(公告)日：2003-05-20

申请号：US10012549

申请日：2001-12-12

Applicant: Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

Inventor： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

IPC: G11C1604

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

公开(公告)号：US06418065B2

公开(公告)日：2002-07-09

申请号：US09883236

申请日：2001-06-19

Applicant: Hiroshi Sato ,  Satoshi Noda ,  Kiichi Manita ,  Shoji Kubono ,  Koji Shigematsu

Inventor： Hiroshi Sato ,  Satoshi Noda ,  Kiichi Manita ,  Shoji Kubono ,  Koji Shigematsu

IPC: G11C700

CPC classification number: G11C5/145 ,  G11C16/12 ,  G11C16/30

Abstract: Disclosed is a semiconductor memory having an internal booster, such as a flash memory, in which a situation that the program cannot escape from a writing operation can be avoided, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory having an internal booster has a voltage detecting circuit (limiter LM) for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time. A control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential and, when it is detected on the basis of counting information of the timer that the predetermined time has elapsed since the booster started the boosting operation, the control circuit applies the boosted voltage to the selected memory cell even if the boosted voltage generated by the booster has not reached the predetermined potential yet.