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    Write/delete process for resistive switching memory components
    1.
    发明授权
    Write/delete process for resistive switching memory components 有权
    电阻式开关存储器组件的写/删除过程

    公开(公告)号：US07457145B2

    公开(公告)日：2008-11-25

    申请号：US11092969

    申请日：2005-03-30

    Applicant: Michael Kund ,  Thomas Happ

    Inventor： Michael Kund ,  Thomas Happ

    IPC: G11C11/00

    CPC classification number: G11C13/0011 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069

    Abstract: The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.

    Abstract translation: 本发明涉及一种用于操作存储器单元的系统，存储器组件和用于操作存储单元的过程，其包括活性材料，其可以通过适当的切换过程改变为或多或少的导电状态，由此该过程包括（a）带来 存储器单元进入或多或少的导电状态，并且在将存储单元改变为或多或少的导电状态之后评估存储单元的状态。

    Method and device for programming CBRAM memory cells
    2.
    发明申请
    Method and device for programming CBRAM memory cells 失效
    用于编程CBRAM存储单元的方法和设备

    公开(公告)号：US20070053224A1

    公开(公告)日：2007-03-08

    申请号：US11515421

    申请日：2006-09-05

    Applicant: Thomas Happ ,  Michael Kund

    Inventor： Thomas Happ ,  Michael Kund

    IPC: G11C16/04

    CPC classification number: G11C13/0011 ,  G11C13/0069 ,  G11C16/3495

    Abstract: Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter the cell content (i.e., the state of bit stored in the memory cell is being changed from a logical 0 to a logical 1 or vice versa).

    Abstract translation: 用于编程导电桥接RAM（CBRAM）存储单元的方法和设备通过确保在重新写入之前擦除存储单元来提高周期稳定性。 可选地，在重写存储器单元的情况下，仅当写入操作将改变单元内容时（即，存储在存储单元中的位的状态正在从逻辑0改变为逻辑1 或相反亦然）。

    Integrated circuit including sub-lithographic structures
    3.
    发明授权
    Integrated circuit including sub-lithographic structures 有权
    集成电路包括亚光刻结构

    公开(公告)号：US07514362B2

    公开(公告)日：2009-04-07

    申请号：US11258367

    申请日：2005-10-26

    Applicant: Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

    Inventor： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

    IPC: H01L21/44

    CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76804 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

    Abstract translation: 可以在图案化层中限定具有基本上小于可以光刻获得的特征尺寸的第一尺寸的开口的方法，包括将由不同于图案形成层的材料制成的牺牲层 图案化层上的预定层厚度。 之后，在牺牲层的表面上施加光致抗蚀剂层，并且在光致抗蚀剂层中光刻地限定具有第二尺寸的开口。 之后，以取决于牺牲层的层厚度以及第一和第二尺寸的方式设置蚀刻角度，并且以蚀刻角度设置蚀刻牺牲层。 之后，蚀刻图形层，去除牺牲层，并将填充材料引入图案化层中产生的开口中。

    Memory Scheduler for Managing Internal Memory Operations
    6.
    发明申请
    Memory Scheduler for Managing Internal Memory Operations 有权
    用于管理内部存储器操作的内存调度器

    公开(公告)号：US20100058018A1

    公开(公告)日：2010-03-04

    申请号：US12202581

    申请日：2008-09-02

    Applicant: Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

    Inventor： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

    IPC: G06F12/00

    CPC classification number: G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431

    Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

    Abstract translation: 集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。 存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。 存储器调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

    Sub-lithographic structures, devices including such structures, and methods for producing the same
    7.
    发明申请
    Sub-lithographic structures, devices including such structures, and methods for producing the same 有权
    亚光刻结构，包括这种结构的装置及其制造方法

    公开(公告)号：US20060091476A1

    公开(公告)日：2006-05-04

    申请号：US11258367

    申请日：2005-10-26

    Applicant: Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

    Inventor： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

    IPC: H01L29/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/00

    CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76804 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

    Abstract translation: 可以在图案化层中限定具有基本上小于可以光刻获得的特征尺寸的第一尺寸的开口的方法，包括将由不同于图案形成层的材料制成的牺牲层 图案化层上的预定层厚度。 之后，在牺牲层的表面上施加光致抗蚀剂层，并且在光致抗蚀剂层中光刻地限定具有第二尺寸的开口。 之后，以取决于牺牲层的层厚度以及第一和第二尺寸的方式设置蚀刻角度，并且以蚀刻角度设置蚀刻牺牲层。 之后，蚀刻图形层，去除牺牲层，并将填充材料引入图案化层中产生的开口中。

    Write/delete process for resistive switching memory components
    8.
    发明申请
    Write/delete process for resistive switching memory components 有权
    电阻式开关存储器组件的写/删除过程

    公开(公告)号：US20050232014A1

    公开(公告)日：2005-10-20

    申请号：US11092969

    申请日：2005-03-30

    Applicant: Michael Kund ,  Thomas Happ

    Inventor： Michael Kund ,  Thomas Happ

    IPC: G11C11/34 ,  G11C13/02 ,  G11C16/02 ,  G11C16/34

    CPC classification number: G11C13/0011 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069

    Abstract: The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by means of an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.

    Abstract translation: 本发明涉及一种用于操作存储器单元的系统，存储器组件和用于操作存储单元的过程，其包括活性材料，其可以通过适当的切换过程改变为或多或少的导电状态，由此该过程包括（a ）使存储器单元进入或多或少的导电状态，并且在将存储单元改变为或多或少的导电状态之后评估存储单元的状态。

    Intergrated circuit for programming resistive memory cells
    10.
    发明授权
    Intergrated circuit for programming resistive memory cells 失效
    用于编程电阻式存储单元的集成电路

    公开(公告)号：US07400528B2

    公开(公告)日：2008-07-15

    申请号：US11515421

    申请日：2006-09-05

    Applicant: Thomas Happ ,  Michael Kund

    Inventor： Thomas Happ ,  Michael Kund

    IPC: G11C11/34

    CPC classification number: G11C13/0011 ,  G11C13/0069 ,  G11C16/3495

    Abstract: Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter the cell content (i.e., the state of bit stored in the memory cell is being changed from a logical 0 to a logical 1 or vice versa).

    Abstract translation: 用于编程导电桥接RAM（CBRAM）存储单元的方法和设备通过确保在重新写入之前擦除存储单元来提高周期稳定性。 可选地，在重写存储器单元的情况下，仅当写入操作将改变单元内容时（即，存储在存储单元中的位的状态正在从逻辑0改变为逻辑1 或相反亦然）。

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