公开(公告)号：US07408222B2

公开(公告)日：2008-08-05

申请号：US11390997

申请日：2006-03-27

Applicant: Rainer Hagenbeck ,  Christoph Ludwig ,  Mark Isler ,  Elard Stein von Kamienski

Inventor： Rainer Hagenbeck ,  Christoph Ludwig ,  Mark Isler ,  Elard Stein von Kamienski

IPC: H01L29/76 ,  H01L21/331

CPC classification number: H01L29/0847 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

Abstract: A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.

Abstract translation: 电荷捕获器件包括具有源极和漏极区域的场效应晶体管。 源区和漏区具有掺杂剂浓度分布，其具有相对于半导体衬底的表面的垂直和横向方向的梯度。 朝向晶体管的耗尽区域的横向的梯度大于朝向阱区域的垂直方向上的梯度。

公开(公告)号：USD566660S1

公开(公告)日：2008-04-15

申请号：US29288970

申请日：2007-06-28

Applicant: Christoph Ludwig ,  Christoph Könnecke

Designer： Christoph Ludwig ,  Christoph Könnecke

公开(公告)号：US07145807B2

公开(公告)日：2006-12-05

申请号：US11072694

申请日：2005-03-04

Applicant: Joachim Deppe ,  Mark Isler ,  Christoph Ludwig ,  Jens-Uwe Sachse ,  Jan-Malte Schley ,  Ricardo Pablo Mikalo

Inventor： Joachim Deppe ,  Mark Isler ,  Christoph Ludwig ,  Jens-Uwe Sachse ,  Jan-Malte Schley ,  Ricardo Pablo Mikalo

IPC: G11C11/34 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C11/5671 ,  G11C16/0475 ,  G11C16/26

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract translation: 提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域，其中信息被存储为有效参数的差异。

公开(公告)号：US07005355B2

公开(公告)日：2006-02-28

申请号：US10735411

申请日：2003-12-12

Applicant: Christoph Kleint ,  Christoph Ludwig ,  Joachim Deppe ,  Jens-Uwe Sachse

Inventor： Christoph Kleint ,  Christoph Ludwig ,  Joachim Deppe ,  Jens-Uwe Sachse

IPC: H01L21/74 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.

Abstract translation: 一种制造半导体器件的方法包括：在半导体本体上形成存储层。 存储层包括第一边界层，中间存储层和第二边界层。 存储层被图案化，使得存储层中的至少一些从半导体主体的第一部分上方移除，并且存储层中的一些从半导体本体的第二部分上移除。 半导体本体的第一部分被掺杂，半导体本体的第二部分被蚀刻。

公开(公告)号：US20050201131A1

公开(公告)日：2005-09-15

申请号：US11124726

申请日：2005-05-09

Applicant: Christoph Ludwig ,  Klaus-Dieter Morhard ,  Christoph Kutter

Inventor： Christoph Ludwig ,  Klaus-Dieter Morhard ,  Christoph Kutter

IPC: H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  G11C11/42

CPC classification number: H01L27/115 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract translation: 半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道 导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于 每个第一轨道导体303和位于其上方的对应的第三轨道导体307之间的电接触305。

公开(公告)号：US07678679B2

公开(公告)日：2010-03-16

申请号：US11414553

申请日：2006-05-01

Applicant: Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

Inventor： Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28247 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.

Abstract translation: 选择性地在垂直装置的垂直侧壁上生长的生长材料在垂直装置的基本上垂直的侧壁上形成侧壁间隔物，其设置在半导体衬底的水平衬底表面上。 可以在垂直装置的垂直侧壁上设置间隔物种子衬垫，以控制选择性生长。 垂直装置可以是场效应晶体管（FET）的栅电极。 利用选择性地生长的侧壁间隔物，FET的重掺杂接触区域可以与栅电极精确地间隔开。 重掺杂的接触区域与栅电极的距离不取决于栅电极的高度。 可以实现重掺杂接触区域和栅电极之间超过150nm的距离，以便于例如DMOS器件的形成。

公开(公告)号：US20100058018A1

公开(公告)日：2010-03-04

申请号：US12202581

申请日：2008-09-02

Applicant: Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

Inventor： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

IPC: G06F12/00

CPC classification number: G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431

Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Abstract translation: 集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。 存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。 存储器调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

公开(公告)号：US20090029512A1

公开(公告)日：2009-01-29

申请号：US12110849

申请日：2008-04-28

Applicant: Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl Heinz Kuesters

Inventor： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl Heinz Kuesters

IPC: H01L21/8247 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

Abstract: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract translation: 一种具有电荷捕获存储单元的半导体存储器及其制造方法。 存储晶体管的每个通道区域的电流流动方向相对于相关字线横向延伸，位线布置在字线的顶侧，并以与之相隔离的方式布置，并且导电的局部 存在源极 - 漏极区域的互连，其在字线之间的间隔中以部分布置并且以与后者的电绝缘并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器中的沟槽中 基质。

公开(公告)号：US07365382B2

公开(公告)日：2008-04-29

申请号：US11067983

申请日：2005-02-28

Applicant: Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl-Heinz Kuesters

Inventor： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl-Heinz Kuesters

IPC: H01L29/76

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract translation: 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。

公开(公告)号：US07323383B2

公开(公告)日：2008-01-29

申请号：US11015747

申请日：2004-12-17

Applicant: Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig

Inventor： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes (2) are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines (18/19) to an extent such that the doped regions (23) are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.

Abstract translation: 在该方法中，蚀刻沟槽（9），并且在其间，位线（8）分别布置在掺杂源极漏极/区域（3）上。 掺杂剂被引入沟槽（9）的底部以便形成掺杂区域（23），以便电修改沟道区域。 存储层被施加，栅电极（2）布置在沟槽壁处。 在沟槽底部的半导体材料在字线（18/19）之间被蚀刻掉到一定程度上，使得掺杂区域（23）在那里被移除到如此大的程度，使得沿着沟槽的相邻存储器单元之间的串扰 降低了。