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    Method for forming a semiconductor product and semiconductor product
    1.
    发明申请
    Method for forming a semiconductor product and semiconductor product 失效
    用于形成半导体产品和半导体产品的方法

    公开(公告)号：US20070001305A1

    公开(公告)日：2007-01-04

    申请号：US11172366

    申请日：2005-06-30

    申请人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    发明人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11568

    摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.

    摘要翻译： 半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。 在其中设置有具有接触孔的第二介质层。 接触孔在第一横向具有宽度。 该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。 导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。 导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

    Multi-bit virtual-ground NAND memory device
    2.
    发明申请
    Multi-bit virtual-ground NAND memory device 有权
    多位虚拟NAND存储器件

    公开(公告)号：US20060245233A1

    公开(公告)日：2006-11-02

    申请号：US11119376

    申请日：2005-04-29

    申请人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

    IPC分类号： G11C17/00

    CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

    摘要： An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

    摘要翻译： 一个电荷捕获多位存储单元的阵列被布置在虚拟地NAND架构中。 存储器单元被Fowler-Nordheim擦除，将电子隧穿到存储器层中。 写入操作通过热空穴注入来实现。 写入电压通过位线施加到两个串联的NAND链。 要编程的存储器单元侧的后续位线保持浮置电位，而另一侧的位线被设置为禁止电压，该禁止电压被提供以阻止寻址的存储器单元的程序干扰 被编程。 电荷俘获存储器单元的虚拟NAND架构能够提高存储密度。

    Semiconductor memory having charge trapping memory cells and fabrication method thereof
    3.
    发明申请
    Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权
    具有电荷捕获存储单元的半导体存储器及其制造方法

    公开(公告)号：US20060192266A1

    公开(公告)日：2006-08-31

    申请号：US11067983

    申请日：2005-02-28

    申请人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl-Heinz Kuesters

    发明人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl-Heinz Kuesters

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

    摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

    摘要翻译： 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。

    Memory element for a semiconductor memory device
    4.
    发明授权
    Memory element for a semiconductor memory device 失效
    用于半导体存储器件的存储元件

    公开(公告)号：US06724038B2

    公开(公告)日：2004-04-20

    申请号：US10223955

    申请日：2002-08-20

    申请人： Thomas Mikolajick

    发明人： Thomas Mikolajick

    IPC分类号： H01L29792

    CPC分类号： G11C11/5671 ,  G11C11/56 ,  H01L29/7887

    摘要： A memory element includes a number of material areas isolated from one another to form at least one area with changed electrical and/or magnetic characteristics in an isolation area, which material areas have or form free charge carriers. An information unit can correspondingly be written to, deleted, and/or read from by influencing the material areas by applying an electrical potential to line devices that are provided in areas.

    摘要翻译： 存储元件包括彼此隔离的多个材料区域，以在隔离区域中形成具有改变的电和/或磁特性的至少一个区域，该区域具有或形成自由电荷载体。 信息单元可以相应地通过对在区域中提供的线路设备施加电势来影响材料区域而被写入，删除和/或读取。

    Semiconductor memory having charge trapping memory cells and fabrication method thereof
    5.
    发明授权
    Semiconductor memory having charge trapping memory cells and fabrication method thereof 失效
    具有电荷捕获存储单元的半导体存储器及其制造方法

    公开(公告)号：US07662687B2

    公开(公告)日：2010-02-16

    申请号：US12110849

    申请日：2008-04-28

    申请人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl Heinz Kuesters

    发明人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl Heinz Kuesters

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

    摘要： A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

    摘要翻译： 一种具有电荷捕获存储单元的半导体存储器及其制造方法。 存储晶体管的每个通道区域的电流流动方向相对于相关字线横向延伸，位线布置在字线的顶侧，并以与之相隔离的方式布置，并且导电的局部 存在源极 - 漏极区域的互连，其在字线之间的间隔中以部分布置并且以与后者的电绝缘并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器中的沟槽中 基质。

    Memory cell arrangements and methods of manufacturing memory cell arrangements
    6.
    发明申请
    Memory cell arrangements and methods of manufacturing memory cell arrangements 有权
    存储单元布置和制造存储单元布置的方法

    公开(公告)号：US20080073694A1

    公开(公告)日：2008-03-27

    申请号：US11526149

    申请日：2006-09-22

    申请人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    发明人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    IPC分类号： H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

    摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

    Evaluation circuit and evaluation method for the assessment of memory cell states
    7.
    发明申请
    Evaluation circuit and evaluation method for the assessment of memory cell states 失效
    用于评估存储单元状态的评估电路和评估方法

    公开(公告)号：US20070086241A1

    公开(公告)日：2007-04-19

    申请号：US11543306

    申请日：2006-10-04

    申请人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    发明人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C27/005

    摘要： An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first assessment result. A second evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses at least one of the at least two analog electrical quantities with a predetermined threshold value and provides a second assessment result.

    摘要翻译： 电子电路装置包括设置用于存储至少两个模拟电量的存储单元。 第一评估电路耦合到存储单元并且被设置成使得其评估至少两个模拟电量并提供第一评估结果。 第二评估电路耦合到存储单元并且被设置成使得其以预定阈值评估至少两个模拟电量中的至少一个并提供第二评估结果。

    Measuring circuit and reading method for memory cells
    8.
    发明申请
    Measuring circuit and reading method for memory cells 失效
    记忆单元的测量电路和读取方法

    公开(公告)号：US20070086240A1

    公开(公告)日：2007-04-19

    申请号：US11542755

    申请日：2006-10-04

    申请人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    发明人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26 ,  G11C16/0475

    摘要： An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.

    摘要翻译： 电子电路装置包括至少一个可存储至少两个电量的存储元件。 开关单元电连接到存储元件并且具有至少一个第一电路路径和第二电路路径。 存储单元具有第一部分存储单元和第二部分存储单元。 每个部分存储单元设置用于存储至少一个电量。 开关单元被设置成使得其可以顺序地将沿着第一电路路径的至少两个电量中的第一个顺序地传递到第一部分存储单元，并且沿着第二电路顺序地通过至少两个电量中的第二个 到第二部分存储单元的电路路径。

    Methods for fabricating non-volatile memory cell array
    9.
    发明申请
    Methods for fabricating non-volatile memory cell array 审中-公开
    制造非易失性存储单元阵列的方法

    公开(公告)号：US20070082446A1

    公开(公告)日：2007-04-12

    申请号：US11246908

    申请日：2005-10-07

    申请人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

    发明人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L27/115 ,  H01L21/76897 ,  H01L27/11568

    摘要： A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

    摘要翻译： 提供了用于制造堆叠的非易失性存储单元的方法。 提供具有形成埋入位线的多个扩散区域的半导体晶片。 电荷捕获层和导电层沉积在半导体晶片的表面上。 在导电层的顶部使用掩模层，形成绝缘层的接触孔。 蚀刻停止层沉积在半导体晶片的表面上。 在蚀刻停止层上方，沉积介电层并图案化以形成接触孔。 随后，接触孔通过蚀刻停止层和绝缘层扩大到埋入位线。