公开(公告)号：US20100264410A1

公开(公告)日：2010-10-21

申请号：US12757605

申请日：2010-04-09

Applicant: Kazumasa Nomoto ,  Mao Katsuhara ,  Akira Yumoto

Inventor： Kazumasa Nomoto ,  Mao Katsuhara ,  Akira Yumoto

IPC: H01L51/10 ,  H01L51/40

CPC classification number: H01L51/102 ,  H01L51/0023 ,  H01L51/0545

Abstract: A method for manufacturing a thin film transistor includes the steps of covering a gate electrode patterned on a substrate with a gate insulating film, forming an organic semiconductor layer and an electrode film on the gate insulating film in that lamination order, and forming a negative type photoresist film on the substrate provided with the organic semiconductor layer and the electrode film and forming a resist pattern, which serves as a mask for forming a source-drain by etching the electrode film, through back surface exposure from the substrate side by using the gate electrode as a light-shielding mask and the following development treatment.

Abstract translation: 一种制造薄膜晶体管的方法包括以栅层绝缘膜覆盖在基板上图案化的栅电极，以栅层绝缘膜形成有机半导体层和电极膜的步骤，并且形成负型 在设置有有机半导体层的基板和电极膜上形成抗蚀剂图案，并且通过使用栅极从基板侧通过背面曝光形成用作通过蚀刻电极膜形成源极 - 漏极的掩模的抗蚀剂图案 电极作为遮光掩模，并进行以下显影处理。

公开(公告)号：US20070026554A1

公开(公告)日：2007-02-01

申请号：US11458573

申请日：2006-07-19

Applicant: Kazumasa Nomoto

Inventor： Kazumasa Nomoto

IPC: H01L21/00 ,  H01L21/84

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L51/0004 ,  H01L51/0005 ,  H01L51/0022 ,  H01L51/0541 ,  H01L51/0545 ,  H01L2251/105

Abstract: A semiconductor device and process for producing same are provided. The process for producing a semiconductor device includes a first embossing step of pressing a stamp having a relief pattern onto a surface of a substrate to form a depression pattern on the surface of the substrate; a second step of feeding an application material composed of a semiconductor material or a conductive material into the depression pattern by printing; and a third step of curing the application material fed by printing.

Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法包括：第一压花步骤，将具有浮雕图案的印模压印到基板的表面上，以在基板的表面上形成凹陷图案; 第二步，通过印刷将由半导体材料或导电材料构成的涂布材料进料到凹陷图案中; 以及固化通过印刷进料的涂布材料的第三步骤。

公开(公告)号：US07023061B2

公开(公告)日：2006-04-04

申请号：US11072505

申请日：2005-03-07

Applicant: Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

Inventor： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

IPC: H01L29/76

CPC classification number: H01L27/11568 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/6656

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract translation: 一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复 在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

公开(公告)号：US20050230766A1

公开(公告)日：2005-10-20

申请号：US11131865

申请日：2005-05-18

Applicant: Kazumasa Nomoto ,  Hiroshi Aozasa ,  Ichiro Fujiwara ,  Shinji Tanaka

Inventor： Kazumasa Nomoto ,  Hiroshi Aozasa ,  Ichiro Fujiwara ,  Shinji Tanaka

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/318 ,  H01L21/762 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/7624

Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.

Abstract translation: 存储器件具有多个电介质膜，其包括其中具有电荷保持能力的电荷存储层CS，并且堆叠在半导体SUB的有源区和多个介电膜上的电极G. 每个电荷存储层CS包括由氮化硅或氮氧化硅制成的第一氮化物膜CS 1和由氮化硅或氮氧化硅制成并且具有比第一氮化物膜CS 1更高的电荷陷阱密度的第二氮化物膜CS 2。 第一氮化物膜CS1通过化学气相沉积形成，该第一气体含有含有预定百分比组成的含氯的第一含硅气体和含氮气体作为原料。 第二氮化物膜CS2通过使用包含比上述预定百分比组成低的氯百分含量的第二含硅气体和含氮气体作为起始材料的第二气体进行化学气相沉积而形成。

公开(公告)号：US06885060B2

公开(公告)日：2005-04-26

申请号：US10101191

申请日：2002-03-19

Applicant: Kazumasa Nomoto ,  Toshio Kobayashi

Inventor： Kazumasa Nomoto ,  Toshio Kobayashi

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

Abstract translation: 一种非易失性半导体存储器件，包括在其表面上具有台阶的第一导电半导体区，形成在每个台阶的上部和底部上的第二导电半导体区域，并且沿垂直于主表面的方向分离 用作源极或漏极的第一导电半导体，其中包含电荷存储装置的栅极电介质膜，空间上离散并形成在第一导电半导体上，以便涂覆至少每一个步骤的侧壁，以及 栅电极形成在栅极电介质膜上。 因此，提供了几乎不会劣化的性能的非易失性半导体存储器件，并且即使当半导体衬底中的半导体存储器件的尺寸缩小时也可以执行每单位存储器件的2位的记录操作 ，以及用于制造非易失性半导体存储器件的工艺。

公开(公告)号：US06376290B1

公开(公告)日：2002-04-23

申请号：US09116119

申请日：1998-07-16

Applicant: Dharam Pal Gosain ,  Jonathan Westwater ,  Miyako Nakagoe ,  Setsuo Usui ,  Kazumasa Nomoto

Inventor： Dharam Pal Gosain ,  Jonathan Westwater ,  Miyako Nakagoe ,  Setsuo Usui ,  Kazumasa Nomoto

IPC: H01L2100

CPC classification number: H01L29/66765 ,  H01L29/78603

Abstract: A method is provided for forming a semiconductor thin film which is free from damage to the film with radiation of a pulse laser beam with the optimum energy value for perfect polycrystallization. For forming an amorphous silicon thin film, a surface of a plastic substrate as a base and insulating layers are each radiated with a pulse laser beam for removing volatile contaminants like a resist as a pretreatment. Damage to the film caused by a gas emitted from the base substrate and the insulating layers resulting from volatile contaminants is thus prevented. A protective layer including a gas barrier layer and a refractory buffer layer is formed on the substrate. Gas penetration from the substrate to the amorphous silicon film is thereby prevented. Conduction of heat produced by energy beam radiation to the substrate is prevented as well. It is possible to increase energy intensity of energy beam radiated for polycrystallization of the amorphous silicon film to the optimal value for perfect polycrystallization.

Abstract translation: 提供了一种用于形成半导体薄膜的方法，该半导体薄膜不会损坏具有用于完美多晶化的最佳能量值的脉冲激光束的辐射。 为了形成非晶硅薄膜，以用作去除挥发性污染物如抗蚀剂的脉冲激光束作为基底和绝缘层的塑料基板的表面各自辐射，作为预处理。 因此防止了由基底衬底发出的气体和由挥发性污染物引起的绝缘层引起的膜损伤。 在基板上形成包括阻气层和难熔缓冲层的保护层。 从而防止了从基板到非晶硅膜的气体渗透。 也可以防止能量束辐射产生的热量传导到基板上。 可以将非晶硅膜的多晶化辐射的能量束的能量强度提高到完美多晶化的最佳值。

公开(公告)号：US06285055B1

公开(公告)日：2001-09-04

申请号：US09381987

申请日：1999-11-29

Applicant: Dharam Pal Gosain ,  Kazumasa Nomoto ,  Jonathan Westwater ,  Miyako Nakagoe ,  Setsuo Usui ,  Takashi Noguchi ,  Yoshifumi Mori

Inventor： Dharam Pal Gosain ,  Kazumasa Nomoto ,  Jonathan Westwater ,  Miyako Nakagoe ,  Setsuo Usui ,  Takashi Noguchi ,  Yoshifumi Mori

IPC: H01L29788

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7883 ,  H01L29/792

Abstract: While a storage region 15 has of many dispersed particulates (dots) (15a), the surface density of the particulates (15a) is set to be higher than that of structural holes (pin holes) produced in a tunnel insulating film (14a), or the number of the particulates (15a) in the storage region (15) is set to five or more. While a conduction region (13c) is formed by a polysilicon layer (13) having a surface roughness of 0.1 nm to 100 nm, the number of the particulates (15a) in the storage region (15) is set to be larger than the number of crystal grains in the conduction region (13c). Even when a defect such as a pin hole occurs in the tunnel insulating film (14a) and charges stored in a part of the particulates are leaked, the charges stored in the particulates formed in a region where no defect occurs are not leaked. Thus, information can be held for a long time.

Abstract translation: 虽然存储区域15具有许多分散的微粒（点）（15a），但是微粒（15a）的表面密度被设定为高于在隧道绝缘膜（14a）中产生的结构孔（针孔）的表面密度， 或存储区域（15）中的微粒（15a）的数量设定为五个以上。 虽然通过表面粗糙度为0.1nm至100nm的多晶硅层（13）形成导电区域（13c），但存储区域（15）中的微粒（15a）的数量被设定为大于数字 的导电区域（13c）中的晶粒。 即使当在隧道绝缘膜（14a）中出现诸如针孔的缺陷，并且存储在一部分微粒中的电荷泄漏时，存储在形成于不发生缺陷的区域中的微粒中的电荷也不会泄漏。 因此，信息可以持续很长时间。

公开(公告)号：US07259433B2

公开(公告)日：2007-08-21

申请号：US11131865

申请日：2005-05-18

Applicant: Kazumasa Nomoto ,  Hiroshi Aozasa ,  Ichiro Fujiwara ,  Shinji Tanaka

Inventor： Kazumasa Nomoto ,  Hiroshi Aozasa ,  Ichiro Fujiwara ,  Shinji Tanaka

IPC: H01L29/72

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/7624

Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.

Abstract translation: 存储器件具有多个电介质膜，其包括其中具有电荷保持能力的电荷存储层CS，并且堆叠在半导体SUB的有源区和多个介电膜上的电极G. 每个电荷存储层CS包括由氮化硅或氮氧化硅制成的第一氮化物膜CS 1和由氮化硅或氮氧化硅制成并且具有比第一氮化物膜CS 1更高的电荷陷阱密度的第二氮化物膜CS 2。 第一氮化物膜CS1通过化学气相沉积形成，该第一气体含有含有预定百分比组成的含氯的第一含硅气体和含氮气体作为原料。 第二氮化物膜CS2通过使用包含比上述预定百分比组成低的氯百分含量的第二含硅气体和含氮气体作为原料的第二气体进行化学气相沉积而形成。

公开(公告)号：US07049655B2

公开(公告)日：2006-05-23

申请号：US11093376

申请日：2005-03-30

Applicant: Kazumasa Nomoto ,  Toshio Kobayashi

Inventor： Kazumasa Nomoto ,  Toshio Kobayashi

IPC: H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US07034356B2

公开(公告)日：2006-04-25

申请号：US11094680

申请日：2005-03-30

Applicant: Kazumasa Nomoto ,  Toshio Kobayashi

Inventor： Kazumasa Nomoto ,  Toshio Kobayashi

IPC: H01L23/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

Abstract: A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.