公开(公告)号：US20130280451A1

公开(公告)日：2013-10-24

申请号：US13976292

申请日：2011-10-05

申请人： Toshio Kobayashi ,  Junji Kono ,  Yutaka Sugiura

发明人： Toshio Kobayashi ,  Junji Kono ,  Yutaka Sugiura

IPC分类号： C08L21/00

CPC分类号： C08L21/00 ,  B62D29/002 ,  C08J9/0023 ,  C08J9/0066 ,  C08J9/06 ,  C08J9/32 ,  C08J2201/026 ,  C08J2203/18 ,  C08J2321/00 ,  C08J2400/22 ,  C08K5/08 ,  C08L2205/03 ,  C08L2666/34 ,  Y10T428/1334

摘要： A paste-like thermally foaming filler contains 2 to 20 parts by weight of an uncrosslinked synthetic rubber. 5 to 30 parts by weight of a partially crosslinked rubber, 0.1 to 5 parts by weight of a quinone-based vulcanizing agent, 0.2 to 1 parts by weight of thermally expandable balloons, 1 to 10 parts by weight of a thermoplastic resin, 20 to 50 parts by weight of a plasticizer, 15 to 50 parts by weight of an inorganic filler, and 2 to 15 parts by weight of a chemical foaming agent. The paste-like thermally foaming filler exhibits high foaming capability even at low temperatures.

摘要翻译： 糊状热发泡填料含有2〜20重量份的未交联的合成橡胶。 5〜30重量份的部分交联的橡胶，0.1〜5重量份的醌类硫化剂，0.2〜1重量份的热膨胀性气囊，1〜10重量份的热塑性树脂，20〜 50重量份的增塑剂，15〜50重量份的无机填料和2〜15重量份的化学发泡剂。 糊状热发泡填料即使在低温下也具有高发泡能力。

公开(公告)号：US08482117B2

公开(公告)日：2013-07-09

申请号：US13181884

申请日：2011-07-13

申请人： Kazutaka Kobayashi ,  Tadashi Arai ,  Toshio Kobayashi

发明人： Kazutaka Kobayashi ,  Tadashi Arai ,  Toshio Kobayashi

IPC分类号： H01L23/04 ,  H01L23/28

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

摘要： An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via.

摘要翻译： 一种电子元件掺合基板及其制造方法，其提供高选择材料的自由度。 电子元件并入基板包括具有基板和电子部件的第一结构。 衬底包括具有第一和第二表面的衬底本体。 第一布线图案形成在第一表面上，并且通过通孔电连接到形成在第二表面上的第二布线图案。 电子部件电连接到第一布线图案。 所述电子部件结合基板包括密封第一结构的密封树脂和通过第二通孔连接到第二布线图案的第三布线图案。

公开(公告)号：US08232639B2

公开(公告)日：2012-07-31

申请号：US12952452

申请日：2010-11-23

申请人： Toshio Kobayashi ,  Takaharu Yamano ,  Takashi Kurihara

发明人： Toshio Kobayashi ,  Takaharu Yamano ,  Takashi Kurihara

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2224/82

摘要： In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.

摘要翻译： 在制造半导体器件安装板的方法中，分别在半导体集成电路上的电极焊盘上形成连接端子。 形成第一绝缘层以覆盖连接端子。 具有粗糙表面的板状介质设置在第一绝缘层上。 板状介质的粗糙表面被压在第一绝缘层上，使每个连接端子的一部分露出。 通过去除板状介质来制造半导体器件。 形成第二绝缘层以覆盖半导体器件的侧表面。 形成布线图案以覆盖第一和第二绝缘层的表面，布线图案电连接到暴露的连接端子部分。

公开(公告)号：US20120013021A1

公开(公告)日：2012-01-19

申请号：US13181884

申请日：2011-07-13

申请人： Kazutaka Kobayashi ,  Tadashi Arai ,  Toshio Kobayashi

发明人： Kazutaka Kobayashi ,  Tadashi Arai ,  Toshio Kobayashi

IPC分类号： H01L23/538 ,  H01L21/78 ,  H01L21/768

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

摘要： An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via.

摘要翻译： 一种电子元件掺合基板及其制造方法，其提供高选择材料的自由度。 电子元件并入基板包括具有基板和电子元件的第一结构。 衬底包括具有第一和第二表面的衬底本体。 第一布线图案形成在第一表面上，并且通过通孔电连接到形成在第二表面上的第二布线图案。 电子部件电连接到第一布线图案。 所述电子部件结合基板包括密封所述第一结构的密封树脂和通过第二通孔连接到所述第二布线图案的第三布线图案。

公开(公告)号：US07989707B2

公开(公告)日：2011-08-02

申请号：US11815580

申请日：2006-12-12

申请人： Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

发明人： Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

IPC分类号： H05K1/16

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

摘要： A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

摘要翻译： 公开了一种制造芯片嵌入式基板的方法。 该方法包括将半导体芯片安装在其上形成有第一布线的第一基板上的第一步骤; 以及将第一基板与形成有第二布线的第二基板接合的第二步骤。 在第二步骤中，将半导体芯片封装在第一基板和第二基板之间，并且在第一布线和第二布线之间形成电连接，以形成连接到半导体芯片的多层布线。

公开(公告)号：US20100112802A1

公开(公告)日：2010-05-06

申请号：US12608383

申请日：2009-10-29

申请人： Toshio Kobayashi ,  Tadashi Arai ,  Takaharu Yamano

发明人： Toshio Kobayashi ,  Tadashi Arai ,  Takaharu Yamano

IPC分类号： H01L21/768

CPC分类号： H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2224/82

摘要： A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer.

摘要翻译： 一种半导体器件嵌入式衬底的制造方法，包括：准备具有第一绝缘层的半导体器件的第一工序; 制备支撑体的第二步骤，以及将半导体器件布置在支撑体的一个表面上; 在所述支撑体的一个表面上形成第二绝缘层的第三步骤; 去除支撑体的第四步骤; 在第一绝缘层和第二绝缘层的表面上形成第一布线图案的第五步骤; 在所述第二绝缘层上形成从所述第一布线图案露出的通孔的第六步骤; 以及形成电连接在第二绝缘层的表面上的第二布线图案的第七步骤。

公开(公告)号：US20090126235A1

公开(公告)日：2009-05-21

申请号：US11659730

申请日：2006-03-16

申请人： Toshio Kobayashi ,  Kazuyoshi Takayama ,  Ken-ichi Ueda ,  Kazuhisa Otomo ,  Shigehito Uetake

发明人： Toshio Kobayashi ,  Kazuyoshi Takayama ,  Ken-ichi Ueda ,  Kazuhisa Otomo ,  Shigehito Uetake

IPC分类号： E02F1/00

CPC分类号： E21B7/00 ,  E21B7/14 ,  E21B7/18 ,  E21B7/24 ,  E21B43/285 ,  E21C45/00

摘要： An excavation technique for a stratum capable of excavating a submerged stratum such as a layer containing an underground resource by using laser irradiation in liquid is provided. In this technique, a laser beam transmitted through laser transmission means 20 is irradiated in liquid 90 in form of a laser beam having a wavelength with high absorptance of the liquid 90 by laser-induced bubble generation means 35, generating a bubble flow 36, thus excavation of a submerged stratum may be carried out by using a laser-induced destruction effect. Moreover, a laser beam 41 having low absorptance of the liquid 90 is irradiated by laser irradiation means 39 and passed through the bubble flow 36, thereby applying a thermal effect to a stratum to destroy rock and excavate the stratum. The destruction effect and the thermal effect also may be cooperatively worked.

摘要翻译： 提供了一种能够通过在液体中使用激光照射来挖掘诸如含有地下资源的层的浸没层的地层的挖掘技术。 在这种技术中，通过激光发射装置35透射的激光束被激光诱导气泡生成装置35以具有高的液体吸收率的波长的激光束的形式在液体90中照射，从而产生气泡流36 浸没层的开挖可以通过使用激光诱发的破坏作用进行。 此外，激光照射装置39照射具有低液体吸收率的激光束41，并通过气泡流36，从而对层施加热效应以破坏岩石并挖掘层。 破坏效果和热效应也可以协同工作。

公开(公告)号：US20080215721A1

公开(公告)日：2008-09-04

申请号：US11966032

申请日：2007-12-28

申请人： Kazunori Saito ,  Hiroki Nogawa ,  Toshio Kobayashi ,  Seiji Moriya

发明人： Kazunori Saito ,  Hiroki Nogawa ,  Toshio Kobayashi ,  Seiji Moriya

IPC分类号： G06F15/173

CPC分类号： H04L63/1416 ,  H04L29/06 ,  H04L43/00 ,  H04L2463/144

摘要： A communication monitoring apparatus for monitoring communication data which are transmitted among a plurality of nodes on a network, includes a detecting section for detecting whether or not a shellcode is included in communication data transmitted and received between at least two nodes within the plurality of nodes and a storing section for storing communication data transmitted from the two nodes as being starting points during a predetermined time, when the detecting section detected the shellcode in communication data.

摘要翻译： 一种用于监视在网络上的多个节点之间发送的通信数据的通信监视装置，包括检测部分，用于检测在所述多个节点之间的至少两个节点之间发送和接收的通信数据中是否包括壳码; 存储部分，用于当检测部分检测到通信数据中的shellcode时，将从两个节点发送的通信数据存储在预定时间内作为起始点。

公开(公告)号：US20080054352A1

公开(公告)日：2008-03-06

申请号：US11846802

申请日：2007-08-29

申请人： Tsutomu Imoto ,  Toshio Kobayashi ,  Takayoshi Kato

发明人： Tsutomu Imoto ,  Toshio Kobayashi ,  Takayoshi Kato

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.

公开(公告)号：US20070145448A1

公开(公告)日：2007-06-28

申请号：US11633292

申请日：2006-12-04

申请人： Toshio Kobayashi ,  Saori Hara

发明人： Toshio Kobayashi ,  Saori Hara

IPC分类号： H01L29/94

CPC分类号： H01L29/792 ,  H01L29/66833 ,  H01L29/7923

摘要： A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on the channel formation region; and a control electrode formed on the laminated insulating film. The laminated insulating film includes a first insulating film, a charge storage film, and a second insulating film in order from the channel formation region side. The control electrode extends to above one of the second semiconductor region and the third semiconductor region. The charge storage film present between an extended portion of the control electrode and the second semiconductor region or the third semiconductor region is removed and a portion where the charge storage film is removed is filled with a third insulating film.

摘要翻译： 非易失性半导体存储器件包括：具有第一导电性的第一半导体区域; 形成具有第二导电性的沟道反转层的沟道形成区域; 具有第二导电性的第二半导体区域; 具有第二导电性的第三半导体区域; 形成在沟道形成区上的叠层绝缘膜; 以及形成在层叠绝缘膜上的控制电极。 叠层绝缘膜从沟道形成区域侧开始依次包括第一绝缘膜，电荷存储膜和第二绝缘膜。 控制电极延伸到第二半导体区域和第三半导体区域中的一个之上。 除去存在于控制电极的延伸部分与第二半导体区域或第三半导体区域之间的电荷存储膜，并且用第三绝缘膜填充电荷存储膜被除去的部分。