公开(公告)号：US07985619B2

公开(公告)日：2011-07-26

申请号：US12608383

申请日：2009-10-29

申请人： Toshio Kobayashi ,  Tadashi Arai ,  Takaharu Yamano

发明人： Toshio Kobayashi ,  Tadashi Arai ,  Takaharu Yamano

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2224/82

摘要： A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer.

摘要翻译： 一种半导体器件嵌入式衬底的制造方法，包括：准备具有第一绝缘层的半导体器件的第一工序; 制备支撑体的第二步骤，以及将半导体器件布置在支撑体的一个表面上; 在所述支撑体的一个表面上形成第二绝缘层的第三步骤; 去除支撑体的第四步骤; 在第一绝缘层和第二绝缘层的表面上形成第一布线图案的第五步骤; 在所述第二绝缘层上形成从所述第一布线图案露出的通孔的第六步骤; 以及形成电连接在第二绝缘层的表面上的第二布线图案的第七步骤。

公开(公告)号：US07937828B2

公开(公告)日：2011-05-10

申请号：US11509684

申请日：2006-08-25

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H05K3/20

CPC分类号： H05K1/186 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/82 ,  H01L2224/83001 ,  H01L2224/85 ,  H01L2224/86 ,  H01L2924/00013 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/53174 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wiring board including an insulating layer where a semiconductor chip is embedded includes: forming, on a supporting board, the insulating layer where the semiconductor chip is embedded and a wiring connected to the semiconductor chip; removing the supporting board by etching; and simultaneously forming first and second reinforcing layers so as to sandwich the insulating layer after removing the supporting board.

摘要翻译： 制造包括半导体芯片的绝缘层的布线板的制造方法包括：在支撑基板上形成嵌入半导体芯片的绝缘层和与半导体芯片连接的布线; 通过蚀刻去除支撑板; 同时形成第一和第二增强层，以便在去除支撑板之后夹住绝缘层。

公开(公告)号：US07786580B2

公开(公告)日：2010-08-31

申请号：US11870743

申请日：2007-10-11

申请人： Yoshihiro Machida ,  Takaharu Yamano

发明人： Yoshihiro Machida ,  Takaharu Yamano

IPC分类号： H01L21/60

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L23/485 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014

摘要： A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.

摘要翻译： 半导体芯片的特征在于包括其上形成有电极焊盘的半导体芯片的结构，形成在各个电极焊盘上的凸起，并且具有突出部分，形成在半导体芯片上的绝缘层和要连接的导电图案 到凸块，其中突出部分的末端插入到导电图案中，并且插入的末端被平坦化。

公开(公告)号：US07772118B2

公开(公告)日：2010-08-10

申请号：US12061768

申请日：2008-04-03

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1461 ,  H05K1/0306 ,  H05K3/007 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4605 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0723 ,  H05K2203/0733 ,  H05K2203/1105 ,  H05K2203/1383 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole.

摘要翻译： 所公开的基板由具有通孔的基部构件，设置在通孔中的贯通孔以及与贯通孔连接的配线构成。 贯通孔包括贯通部，该贯通部在基部构件的两侧设置有设置在贯通孔中的两端，从基体突出的第一突起，该第一突起形成在贯通部的第一端上，从而 连接到布线，以及形成在穿透部的第二端上的从基部构件突出的第二突起。 第一突起和第二突起比通孔的直径宽。

公开(公告)号：US07763977B2

公开(公告)日：2010-07-27

申请号：US11984596

申请日：2007-11-20

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00

摘要： It is a semiconductor device that has a semiconductor chip on which an electrode pad is formed, an electric connection member formed on the electrode pad, an insulating layer formed on the semiconductor chip, and an electrically conductive pattern connected to the electric connection member. An opening portion corresponding to the electric connection member is formed in the conductive pattern. The conductive pattern is electrically connected to the electric connection member by an electrically conducting paste embedded in the opening portion.

摘要翻译： 它是具有形成有电极焊盘的半导体芯片的半导体器件，形成在电极焊盘上的电连接部件，形成在半导体芯片上的绝缘层和连接到电连接部件的导电图案。 在导电图案中形成对应于电连接构件的开口部。 导电图案通过嵌入在开口部分中的导电糊电连接到电连接构件。

公开(公告)号：US20090183911A1

公开(公告)日：2009-07-23

申请号：US12348514

申请日：2009-01-05

申请人： Masahiro SUNOHARA ,  Kei Murayama ,  Takaharu Yamano

发明人： Masahiro SUNOHARA ,  Kei Murayama ,  Takaharu Yamano

IPC分类号： H05K1/11 ,  B05D5/12

CPC分类号： H05K3/4092 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2924/01322 ,  H05K3/062 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0311 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/1059 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wiring board includes an external connection terminal of a cylindrical shape, in which an electrode terminal of the electronic component to be mounted is fitted. In one configuration, a portion of the external connection terminal is electrically connected to a pad portion formed on an electronic component mounting surface side of the wiring board, and the external connection terminal is curvedly formed in such a shape that the outer periphery of the electrode terminal comes into close contact with the inner periphery of the middle portion of the external connection terminal when the electrode terminal is inserted into the external connection terminal.

摘要翻译： 布线基板包括一个圆柱形外部连接端子，其中安装有电子元件的电极端子。 在一种构造中，外部连接端子的一部分电连接到形成在布线板的电子部件安装表面侧上的焊盘部分，并且外部连接端子被弯曲地形成为使得电极的外周 当电极端子插入外部连接端子时，端子与外部连接端子的中间部分的内周紧密接触。

公开(公告)号：US20090127665A1

公开(公告)日：2009-05-21

申请号：US12273901

申请日：2008-11-19

申请人： Takaharu Yamano ,  Yoshihiro Machida

发明人： Takaharu Yamano ,  Yoshihiro Machida

IPC分类号： H01L21/304 ,  H01L23/58

CPC分类号： H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/10 ,  H01L2224/02333 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014

摘要： A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position.

摘要翻译： 一种制造半导体器件的方法，具有制备具有多个半导体芯片形成区域的半导体衬底和布置在多个半导体芯片形成区域之间并包括衬底切割位置的划线区域的准备步骤，半导体芯片形成步骤 在所述多个半导体芯片形成区域上形成具有电极焊盘的半导体芯片，在所述半导体芯片上形成第一绝缘层和所述半导体基板的划线区域的第一绝缘层形成步骤，形成第二绝缘层形成工序， 除了与基板切断位置对应的区域之外的第一绝缘层上的绝缘层，以及在基板切断位置切断半导体基板的切断工序。

公开(公告)号：US07521283B2

公开(公告)日：2009-04-21

申请号：US11257717

申请日：2005-10-25

申请人： Yoshihiro Machida ,  Takaharu Yamano

发明人： Yoshihiro Machida ,  Takaharu Yamano

IPC分类号： H01L21/00

CPC分类号： H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00

摘要： A manufacturing method of a chip integrated substrate is disclosed. The manufacturing method includes a first step that forms a wiring structure to be connected to a semiconductor chip on a first core substrate; a second step that disposes the semiconductor chip on a second core substrate; and a third step that bonds the first core substrate on which the wiring structure is formed to the second core substrate on which the semiconductor chip is disposed. In addition, the manufacturing method includes a step that removes the first core substrate after the third step and a step that removes the second core substrate after the third step.

摘要翻译： 公开了一种芯片集成基板的制造方法。 该制造方法包括：形成与第一芯基板上的半导体芯片连接的布线结构的第一工序; 将所述半导体芯片配置在第二芯基板上的第二工序; 以及将其上形成有布线结构的第一芯基板结合到其上设置有半导体芯片的第二芯基板的第三步骤。 此外，该制造方法包括在第三步骤之后去除第一芯基板的步骤和在第三步骤之后去除第二芯基板的步骤。

公开(公告)号：US20090001570A1

公开(公告)日：2009-01-01

申请号：US12142053

申请日：2008-06-19

申请人： Takaharu YAMANO

发明人： Takaharu YAMANO

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/02313 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present disclosure relates to a method of manufacturing an electronic device in which a plurality of first bumps serving as external connection terminals are formed on a conductive pattern. The method includes: (a) forming a second bump having a projection portion on an electrode pad formed on a substrate; (b) forming an insulating layer on the substrate; (c) exposing a portion of the projection portion from an upper surface of the insulating layer; (d) forming a flat stress absorbing layer in a bump providing area, in which the first bumps are provided, on the insulating layer; (e) forming a first conductive layer on the insulating layer and the stress absorbing layer and the exposed portion of the projection portion; (f) forming a second conductive layer by an electroplating using the first conductive layer as a power feeding layer; (g) forming the conductive pattern by patterning the second conductive layer; and (h) forming the first bumps on the conductive pattern formed on the stress absorbing layer.

摘要翻译： 本发明涉及一种制造电子器件的方法，其中在导电图案上形成多个用作外部连接端子的第一凸起。 该方法包括：（a）在形成在基板上的电极焊盘上形成具有突出部分的第二凸块; （b）在基板上形成绝缘层; （c）从绝缘层的上表面露出突出部分的一部分; （d）在所述绝缘层上在设置有所述第一凸块的凸块供给区域中形成平坦的应力吸收层; （e）在绝缘层和应力吸收层和突出部分的暴露部分上形成第一导电层; （f）使用第一导电层作为供电层通过电镀形成第二导电层; （g）通过图案化所述第二导电层形成所述导电图案; 和（h）在形成在应力吸收层上的导电图案上形成第一凸块。

公开(公告)号：US20080315414A1

公开(公告)日：2008-12-25

申请号：US12140706

申请日：2008-06-17

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L2224/02313 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/48 ,  H01L2924/00

摘要： There are provided the steps of forming a bump 104 having a protruded portion 104B on an electrode pad 103 formed on a substrate 101A, forming an insulating layer 105 on the substrate 101A and exposing a part of the protruded portion 104B to an upper surface of the insulating layer 105, forming a first conductive pattern 107 by using a depositing process in the upper surface of the insulating layer 105 and an exposed part of the protruded portion 104B, carrying out electrolytic plating by using the first conductive pattern 107 as a feeding layer, thereby forming a second conductive pattern 108, and patterning the second conductive pattern 108 to form a conductive pattern 106 connected to the bump 104.

摘要翻译： 提供了在形成在基板101A上的电极焊盘103上形成具有突出部分104B的凸块104的步骤，在基板101A上形成绝缘层105，并将突出部分104B的一部分暴露于 绝缘层105，通过使用绝缘层105的上表面中的沉积工艺和突出部分104B的暴露部分形成第一导电图案107，通过使用第一导电图案107作为馈送层进行电解电镀， 从而形成第二导电图案108，并且图案化第二导电图案108以形成连接到凸块104的导电图案106。