知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

270 records (took 0.023 seconds)

    Self-aligned cylindrical stacked capacitor DRAM cell
    61.
    发明授权
    Self-aligned cylindrical stacked capacitor DRAM cell 失效
    自对准圆柱形堆叠电容器DRAM单元

    公开(公告)号：US5192702A

    公开(公告)日：1993-03-09

    申请号：US811991

    申请日：1991-12-23

    Applicant: Horng-Huei Tseng

    Inventor： Horng-Huei Tseng

    IPC: H01L27/108

    CPC classification number: H01L27/10817

    Abstract: A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas. An etch mask is now formed on the second polysilicon layer and the second polysilicon layer is anisotropically etching to form a shell-shaped second polysilicaon layer. A capacitor dielectric layer is formed over the shell-shaped second polysilicon layer. A third polysilicon layer is deposited and patterned as the top storage node electrode to complete the stacked capacitors. The etch mask can either be formed in part by a lateral etching of a resist mask or is formed in part by use of a sidewall spacer structure and mask. The first insulator layer is patterned to expose the source/drain structures to electrical contact either before or after the deposition of the second polysilicon layer.

    Abstract translation: 制造具有高电容层叠电容器的动态随机存取存储器的方法是通过在半导体衬底的表面上选择性地形成相对厚的场氧化物区域，同时留出用于制造场效应器件的器件区域。 在器件区域中的衬底上形成栅极电介质层。 相对厚的第一多晶硅层沉积在场氧化物区域和器件区域上。 去除第一多晶硅层的部分，同时留下用于器件区域中的栅极结构的部分，以及场氧化物区域上的部分。 至少部分由氮化硅构成的第一绝缘体层形成在器件和场氧化物区域上。 现在通过首先在器件和场氧化物区域上沉积第二多晶硅层来形成堆叠的电容器。 现在在第二多晶硅层上形成蚀刻掩模，并且第二多晶硅层进行各向异性蚀刻以形成壳形第二聚硅氧烷层。 在壳状第二多晶硅层上形成电容器电介质层。 沉积第三多晶硅层并将其图案化为顶部存储节点电极以完成堆叠的电容器。 蚀刻掩模可以部分地通过抗蚀剂掩模的横向蚀刻形成，或者部分地通过使用侧壁间隔物结构和掩模形成。 图案化第一绝缘体层，以在第二多晶硅层沉积之前或之后使源极/漏极结构暴露于电接触。

    VEHICLE SUMMON SYSTEM
    62.
    发明申请
    VEHICLE SUMMON SYSTEM 审中-公开

    公开(公告)号：US20190018418A1

    公开(公告)日：2019-01-17

    申请号：US15648535

    申请日：2017-07-13

    Applicant: Horng-Huei TSENG ,  Kuo-Ching CHIANG

    Inventor： Horng-Huei TSENG ,  Kuo-Ching CHIANG

    IPC: G05D1/02 ,  H04W4/04 ,  G05D1/00

    Abstract: The present invention discloses a safety system for a user vehicle including a controller, a display, an inter-vehicle wireless communication module coupled to the controller to receive GPS data of other vehicle around the user vehicle. A surrounding object pattern generator is coupled to the controller to generate a surrounding object pattern based on the GPS data of the other vehicle.

    Anchored damascene structures
    65.
    发明申请
    Anchored damascene structures 有权
    锚定镶嵌结构

    公开(公告)号：US20070085209A1

    公开(公告)日：2007-04-19

    申请号：US11252498

    申请日：2005-10-18

    Applicant: David Lu ,  Horng-Huei Tseng ,  Syun-Ming Jang

    Inventor： David Lu ,  Horng-Huei Tseng ,  Syun-Ming Jang

    IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC classification number: H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps

    Abstract translation: 埋置在多密度电介质层中的锚定导电镶嵌体及其形成方法，所述锚定导电镶嵌体包括具有延伸穿过介电层厚度的开口的介电层; 其中所述电介质层包括至少一个相对较高密度的部分和相对较低的密度部分，所述较低密度部分形成所述电介质层的连续主要部分; 并且其中相对较低密度部分中的开口具有与相对较高密度部分相比较大的横向尺寸以形成锚固步骤

    Method of selectively making copper using plating technology
    70.
    发明授权
    Method of selectively making copper using plating technology 有权
    使用电镀技术选择性制作铜的方法

    公开(公告)号：US06841466B1

    公开(公告)日：2005-01-11

    申请号：US10672395

    申请日：2003-09-26

    Applicant: Chen-Hua Yu ,  Horng-Huei Tseng

    Inventor： Chen-Hua Yu ,  Horng-Huei Tseng

    IPC: H01L21/768 ,  H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/7684 ,  H01L21/76879

    Abstract: A method of forming a more uniform copper interconnect layer is described. A dielectric layer, electroconductive (EC) layer, and a photoresist layer are sequentially deposited on a substrate. An opening in the photoresist is etched through the dielectric layer while the EC layer serves as a hard mask. Following deposition of a diffusion barrier layer and copper seed layer on the EC layer and in the opening, the copper seed layer is removed above the EC layer by a first CMP step. The EC layer serves as a CMP stop to protect the dielectric layer and provides a more uniform surface for subsequent steps. Copper is selectively deposited on the seed layer within the opening. A second CMP step lowers the copper layer to be coplanar with the dielectric layer and removes the EC layer. The resulting copper interconnect layer has a more uniform thickness and surface for improved performance.

    Abstract translation: 描述形成更均匀的铜互连层的方法。 电介质层，导电（EC）层和光致抗蚀剂层顺序沉积在基片上。 通过介电层蚀刻光致抗蚀剂中的开口，而EC层用作硬掩模。 在EC层和开口中沉积扩散阻挡层和铜籽晶层之后，通过第一CMP步骤在EC层上方去除铜籽晶层。 EC层用作CMP阻挡层，以保护电介质层，并为后续步骤提供更均匀的表面。 铜选择性地沉积在开口内的种子层上。 第二CMP步骤降低铜层与电介质层共面并去除EC层。 所得的铜互连层具有更均匀的厚度和表面以提高性能。

Patent Agency Ranking