公开(公告)号：US09800247B2

公开(公告)日：2017-10-24

申请号：US15181646

申请日：2016-06-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: H03K19/177 ,  H03K19/0185 ,  G06F9/445 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/12 ,  H03K19/173

CPC classification number: H03K19/1776 ,  G06F9/445 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/12 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/0409 ,  H03K19/018507 ,  H03K19/1735 ,  H03K19/17728

Abstract: In a processor or the like including a reconfigurable (RC) circuit, the RC circuit is used to form a test circuit to test a core, a cache memory, or the like, and then part of the RC circuit is used as an auxiliary cache memory. When a memory can store data after stop of power supply, a startup routine program (SRP) of the processor can be stored therein. For example, after the test, an SRP is loaded to a memory in the RC circuit from an external ROM or the like, and when power is resupplied to the processor, a startup operation is performed using the loaded SRP. When the processor is in a normal operation state, this memory is used as an auxiliary cache memory and the SRP is overwritten. The SRP is loaded to the memory again at the end of use of the processor.

公开(公告)号：US09786388B1

公开(公告)日：2017-10-10

申请号：US14050249

申请日：2013-10-09

Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Inventor： Amir Nassie

IPC: G11C29/56 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G06F12/02 ,  G06F11/10 ,  G11C29/44

CPC classification number: G06F11/1068 ,  G06F12/0246 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/72 ,  G11C29/804 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4002 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: A system, computer readable medium and a method. The method may include sending input data to a NAND flash memory unit that comprises the NAND flash memory array and instructing the NAND flash memory unit to write input data to the NAND flash memory array to provide programmed data; reading from the NAND flash memory array the programmed data to provide read data; comparing the input data and the read data to provide column errors statistics at a column resolution; and defining, by a flash memory controller, bad columns of the NAND flash memory array in response to the column error statistics.

公开(公告)号：US09786381B2

公开(公告)日：2017-10-10

申请号：US15232791

申请日：2016-08-09

Applicant: Toshiba Memory Corporation

Inventor： Yoshiki Terabayashi

IPC: G11C7/00 ,  G11C16/34 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/12

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C29/04 ,  G11C29/1201 ,  G11C29/4401 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/1204 ,  G11C2029/1208

Abstract: A semiconductor memory device includes a memory cell unit including a plurality of blocks, each of the blocks including a plurality of pages, and a circuit configured to count a number of activated or non-activated memory cells in one or more pages when a first voltage is applied to gates of memory cells of said one or more pages to read data therefrom, count a number of activated or non-activated memory cells in said one or more pages when a second voltage different from the first voltage is applied to the gates of the memory cells of said one or more pages to read data therefrom, compare the counted numbers, and store, in a register, data about deterioration of the memory cells of said one or more pages depending on a comparison result.

公开(公告)号：US09785493B1

公开(公告)日：2017-10-10

申请号：US15373887

申请日：2016-12-09

Applicant: SanDisk Technologies LLC

Inventor： Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/16 ,  G06F11/07 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

CPC classification number: G11C16/3427 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3481 ,  G11C16/349 ,  G11C29/025 ,  G11C29/028 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

Abstract: A memory device and associated techniques provide a read recovery of data in case of a short circuit between word lines. When cells of a recovery word line WLrec are successfully programmed but cells of an adjacent work line WLrec+1 are not successfully programmed, the data of the cells of WLrec can be recovered. The cells of WLrec+1 are erased so that a low pass voltage on WLrec+1 is adequate to provide these cells in a conductive state during the recovery read of WLrec. Capacitive coupling between the word lines which shifts the apparent threshold voltage of the cells on WLrec is reduced so that a more accurate recovery read can be performed. Read voltages on WLrec can be upshifted compared to baseline read voltages.

公开(公告)号：US20170287542A1

公开(公告)日：2017-10-05

申请号：US15505795

申请日：2015-08-21

Applicant: Alacrity Semiconductors, Inc.

Inventor： James Lin ,  Tso-Ping Ma

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C7/1006 ,  G11C11/22 ,  G11C29/4401 ,  G11C29/787 ,  G11C2029/0409 ,  G11C2029/4402 ,  H01L27/105

Abstract: Methods and apparatus for programming a ferroelectric memory according to various desired and constraining characteristics, such as the retention of the data written to the memory, the endurance of the memory itself, both retention and endurance, power consumption, constraints on available voltage levels, etc. The characteristics of the signal used to write the data to memory (e.g., voltage, power, etc.) are selected to as to satisfy the various desired and constraining characteristics.

公开(公告)号：US20170286206A1

公开(公告)日：2017-10-05

申请号：US15083528

申请日：2016-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan FISCHER-TOUBOL ,  Ronen GAZIT ,  Afief HALUMI ,  Lior SHLOMOV ,  Ariel WAIZEL

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0703 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/079 ,  G11C2029/0409

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include configuring, at a first time, a clustered storage system comprising multiple modules to store and process storage requests for respective sets of data objects. While processing the storage requests, respective subsets of the data objects having one or more data errors are identified, and at a second time subsequent to the first time, respective modules storing each of the data objects having at least one data error are identified. computing, based on the identified modules, a frequency distribution of the identified data errors in the data objects over the multiple modules. Based on the frequency distribution, a failure in a given module is identified, and the identified module is removed from the storage system. In some embodiments, prior to the second time, the data objects can be redistributed among the modules of the storage system.

公开(公告)号：US09779818B2

公开(公告)日：2017-10-03

申请号：US14794862

申请日：2015-07-09

Applicant: APPLE INC.

Inventor： Barak Baum ,  Alex Radinski ,  Eyal Gurgi ,  Naftali Sommer ,  Tsafrir Kamelo

IPC: G11C7/14 ,  G11C29/52 ,  G11C29/04 ,  G11C29/02 ,  G11C27/00 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G06F11/07 ,  G11C16/10 ,  G11C16/28 ,  G11C29/42 ,  G11C16/26

CPC classification number: G11C16/10 ,  G06F11/1012 ,  G11C7/14 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3459 ,  G11C27/005 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/0409

Abstract: A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.

公开(公告)号：US20170277455A1

公开(公告)日：2017-09-28

申请号：US15418389

申请日：2017-01-27

Applicant: Renesas Electronics Corporation

Inventor： Takeshi Sunada ,  Daisuke Oshida ,  Makoto Yabuuchi

IPC: G06F3/06 ,  G11C29/44 ,  G11C29/12 ,  G06F11/30 ,  G06F11/34

CPC classification number: G11C29/44 ,  G06F11/008 ,  G06F11/2284 ,  G06F11/3072 ,  G06F2201/81 ,  G11C16/349 ,  G11C17/18 ,  G11C29/12005 ,  G11C29/42 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0409

Abstract: The disclosed invention can provide a semiconductor device, a lifetime prediction system, and a lifetime prediction method enabling it to notify a user that a semiconductor device is likely to become faulty, before the semiconductor device becomes faulty. A semiconductor device includes functional units and a lifetime prediction circuit. The lifetime prediction circuit acquires a deterioration degree indicating a degree of how each functional unit deteriorates, using a signal that is output from each functional unit. The lifetime prediction circuit executes processing to make a notification that the semiconductor device is close to its lifetime, if the deterioration degree is more than a first threshold.

公开(公告)号：US20170262206A1

公开(公告)日：2017-09-14

申请号：US15487975

申请日：2017-04-14

Applicant: Infineon Technologies AG

Inventor： Mihai-Alexandru Ionescu ,  Christoph Schroers ,  Davide Cassata ,  Hubert Fischer ,  Wolfgang Horn ,  Razvan-Catalin Mialtu ,  Radu Mihaescu

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G01D3/022 ,  G01D9/005 ,  G01D9/06 ,  G01D18/008 ,  G06F1/30 ,  G06F3/064 ,  G06F3/0673 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: An information storage circuit having a first memory portion configured to store a first validity bit and first data; a second memory portion configured to store a second validity bit and second data; and a subcircuit configured to: write the first data to the first memory portion and the second data to the second memory portion sequentially; and set the first and second validity bits to indicate which of the first data and second data is valid.

公开(公告)号：US09761326B2

公开(公告)日：2017-09-12

申请号：US15065092

申请日：2016-03-09

Applicant: Toshiba Memory Corporation

Inventor： Yu Nakanishi ,  Daisuke Iwai ,  Kiwamu Watanabe ,  Kenji Funaoka ,  Tetsuya Sunata ,  Keigo Hara ,  Marie Takada

IPC: G11C29/00 ,  G11C29/02 ,  G06F11/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C29/028 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/222 ,  G11C29/023 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.