Abstract:
A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.
Abstract:
A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.
Abstract:
A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.
Abstract:
A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.
Abstract:
A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
Abstract:
A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.
Abstract:
A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.
Abstract:
A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.
Abstract:
An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.
Abstract:
A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
Abstract translation:一个设备包括一个存储器和一个读/写(R / W)单元。 存储器包括耦合到公共电荷陷阱层的多个门。 R / W单元被配置为通过在公共电荷陷阱层中创建和读取一组充电区域来对存储器进行编程和读取,其中集合中的至少一个给定区域不是唯一地与 大门。