公开(公告)号：US12073093B2

公开(公告)日：2024-08-27

申请号：US18449647

申请日：2023-08-14

申请人： KIOXIA CORPORATION

发明人： Daisuke Hashimoto

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F1/26 ,  G06F11/10 ,  G11C5/14 ,  G11C29/52

CPC分类号： G06F3/0619 ,  G06F3/0614 ,  G06F3/0625 ,  G06F12/0246 ,  G06F1/266 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0683 ,  G06F3/0688 ,  G06F11/1068 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/263 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C5/144 ,  G11C5/147 ,  G11C5/148 ,  G11C29/52 ,  Y02D10/00

摘要： A memory system includes an interface circuit configured to connect to a host device, a controller electrically connected to the interface circuit, and a nonvolatile semiconductor memory electrically connected to the controller. The controller is configured to transmit a first response in response to a power supplied from the host device via the interface circuit, upon receipt of a first command from the host device after transmitting the first response, determine a status of data stored in the nonvolatile semiconductor memory, and transmit to the host device a second response including the determined status of the data stored in the nonvolatile semiconductor memory.

公开(公告)号：US12072796B2

公开(公告)日：2024-08-27

申请号：US18138378

申请日：2023-04-24

申请人： Kioxia Corporation

发明人： Shinichi Kanno

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0891

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/10 ,  G06F12/0253 ,  G06F12/0292 ,  G06F12/0891 ,  G06F2212/7201

摘要： According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.

公开(公告)号：US12072622B2

公开(公告)日：2024-08-27

申请号：US17897030

申请日：2022-08-26

申请人： KIOXIA CORPORATION

发明人： Hirokazu Miyoshi ,  Masayuki Hatano

IPC分类号： G03F7/00 ,  H01L21/02

CPC分类号： G03F7/0002 ,  H01L21/02348

摘要： According to one embodiment, an imprint method for a substrate having a plurality of shot regions includes performing a first process on each target shot region in the plurality of shot regions and performing a second process on a non-target shot region in the plurality of shot regions. The first process includes pressing a template against resin in the target shot region to transfer a pattern to the resin, curing the resin, and releasing the template from the cured resin while supplying inert gas towards the substrate from an outer edge side of the template. The second process includes causing the template to approach the non-target shot region without coming into contact with resin in the non-target shot region, and moving the template away from the resin in the non-target shot region while supplying inert gas towards the substrate from the outer edge side of the template.

公开(公告)号：US12072273B2

公开(公告)日：2024-08-27

申请号：US17841819

申请日：2022-06-16

申请人： Kioxia Corporation

发明人： Kasumi Okabe ,  Takeshi Higuchi

IPC分类号： G01N15/08

CPC分类号： G01N15/082 ,  G01N15/0806 ,  G01N2015/0846

摘要： A measuring method includes: placing resist 20 on a surface of a test film; pressing a template 30 against the resist 20 placed on the surface of the test film; measuring a size of a void formed in the resist 20 after pressing the template 30 against the resist 20; and determining gas permeability of the test film based on the size of the void.

公开(公告)号：US20240282618A1

公开(公告)日：2024-08-22

申请号：US18433810

申请日：2024-02-06

申请人： Kioxia Corporation

发明人： Kentaku ARAI

IPC分类号： H01L21/687 ,  H01L21/67

CPC分类号： H01L21/68735 ,  H01L21/67069 ,  H01L21/68707 ,  H01L21/68742 ,  H01L21/68757

摘要： A jig includes a main body having a form of a semiconductor wafer. A first face of the main body has a groove of a circular form or an arc form. A semiconductor manufacturing apparatus according to the embodiment includes a chamber that houses a semiconductor wafer and processes the semiconductor wafer under reduced pressure. A stage is disposed inside the chamber, and the semiconductor wafer can be placed on the stage. A supply holds the jig which includes the main body having the shape of the semiconductor wafer and the groove provided in the first face of the main body. A transfer unit transfers the jig from the stage to the supply.

公开(公告)号：US20240282384A1

公开(公告)日：2024-08-22

申请号：US18612239

申请日：2024-03-21

申请人： Kioxia Corporation

发明人： Takashi MAEDA

IPC分类号： G11C16/16 ,  G11C5/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H02J50/12 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H02J50/12 ,  H10B43/27 ,  H10B43/35 ,  G11C5/145 ,  G11C16/30 ,  H02J2310/48

摘要： When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the 10 selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US20240281580A1

公开(公告)日：2024-08-22

申请号：US18582447

申请日：2024-02-20

申请人： Kioxia Corporation

发明人： Atsushi NAKAYAMA

IPC分类号： G06F30/3308 ,  G06F30/3323

CPC分类号： G06F30/3308 ,  G06F30/3315

摘要： A library creation device for creating a library for circuit analysis of a semiconductor integrated circuit, includes a storage device, and a processor configured to: using a computer model corresponding to the integrated circuit, execute a simulation multiple times for calculating an expected value indicating an electrical characteristic of the integrated circuit and a variation of the expected value, for each of a plurality of sets of input parameters; and generate a library including the expected value and the variation for each of the sets of input parameters and statistical processing information indicating a condition of the executed simulation, and store the generated library in the storage device.

公开(公告)号：US20240281149A1

公开(公告)日：2024-08-22

申请号：US18645697

申请日：2024-04-25

申请人： Kioxia Corporation

发明人： Junji YANO ,  Hidenori MATSUZAKI ,  Kosuke HATSUDA

IPC分类号： G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G11C7/20 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC分类号： G06F3/0619 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0685 ,  G06F11/1456 ,  G06F11/1471 ,  G06F12/0246 ,  G11C7/20 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/105 ,  G06F11/1469 ,  G06F2201/84 ,  G06F2212/7201 ,  G06F2212/7207

摘要： A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

公开(公告)号：US12069962B2

公开(公告)日：2024-08-20

申请号：US17196737

申请日：2021-03-09

申请人： Kioxia Corporation

发明人： Tsuyoshi Kondo ,  Nobuyuki Umetsu ,  Yasuaki Ootera ,  Tsutomu Nakanishi ,  Shigeyuki Hirayama

IPC分类号： H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC分类号： H10N50/80 ,  H10B61/22 ,  H10N50/01

摘要： A magnetic memory according to an embodiment includes: a first wiring and a second wiring; a nonmagnetic conductor extending in a first direction; a first magnetic member including a first portion electrically connected to the first wiring and a second portion electrically connected to the second wiring, the first magnetic member extending in the first direction from the first portion to the second portion to surround the nonmagnetic conductor; an insulation portion disposed between the nonmagnetic conductor and the first magnetic member; and a controller electrically connected to the nonmagnetic conductor, the first wiring, and the second wiring.

公开(公告)号：US12069872B2

公开(公告)日：2024-08-20

申请号：US18231304

申请日：2023-08-08

申请人： Kioxia Corporation

发明人： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC分类号： G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

摘要： A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.