公开(公告)号：US11121041B2

公开(公告)日：2021-09-14

申请号：US16684765

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zoe Chen ,  Ching-Hwanq Su ,  Cheng-Lung Hung ,  Cheng-Yen Tsai ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Weng Chang ,  Wei-Chin Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10

Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.

公开(公告)号：US11075275B2

公开(公告)日：2021-07-27

申请号：US15909815

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Ching-Hwanq Su ,  Da-Yuan Lee ,  Ji-Cheng Chen ,  Kuan-Ting Liu ,  Tai-Wei Hwang ,  Chung-Yi Su

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/285 ,  H01L29/51 ,  H01L21/8234

Abstract: Certain embodiments of a semiconductor device and a method of forming a semiconductor device comprise forming a high-k gate dielectric layer over a short channel semiconductor fin. A work function metal layer is formed over the high-k gate dielectric layer. A seamless metal fill layer is conformally formed over the work function metal layer.

公开(公告)号：US20210134667A1

公开(公告)日：2021-05-06

申请号：US17120696

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsueh Wen Tsau ,  Chia-Ching Lee ,  Cheng-Lung Hung ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

公开(公告)号：US20200321252A1

公开(公告)日：2020-10-08

申请号：US16907570

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Wei-Chin Lee ,  Shih-Hang Chiu ,  Chia-Ching Lee ,  Hsueh Wen Tsau ,  Cheng-Yen Tsai ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

公开(公告)号：US10700177B2

公开(公告)日：2020-06-30

申请号：US15964352

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Yi-Hsiang Chao ,  Kuan-Yu Yeh ,  Kan-Ju Lin ,  Chun-Wen Nieh ,  Huang-Yi Huang ,  Chih-Wei Chang ,  Ching-Hwanq Su

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/306 ,  H01L29/08

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.

公开(公告)号：US09935173B1

公开(公告)日：2018-04-03

申请号：US15363455

申请日：2016-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Chia-Ching Lee ,  Hsueh-Wen Tsau ,  Chun-Yuan Chou ,  Ching-Hwanq Su

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76254 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes patterning a semiconductor substrate to form a fin structure. The method also includes forming a sacrificial material over the fin structure. The method further includes forming spacer elements adjoining sidewalls of the sacrificial material. Furthermore, the method includes removing the sacrificial material so that a trench is formed between the spacer elements. The method also includes forming a gate dielectric layer in the trench. The method further includes forming a work function layer in the trench to cover the gate dielectric layer. In addition, the method includes depositing a tungsten bulk layer with a precursor to fill the trench. The precursor includes a tungsten-containing material that is substantially free of fluoride.

公开(公告)号：US20240379776A1

公开(公告)日：2024-11-14

申请号：US18783501

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ya-Huei Li ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L29/40 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

公开(公告)号：US12142530B2

公开(公告)日：2024-11-12

申请号：US17365057

申请日：2021-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Ching-Hwanq Su

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US12021147B2

公开(公告)日：2024-06-25

申请号：US18064350

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/7851 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

公开(公告)号：US12021130B2

公开(公告)日：2024-06-25

申请号：US18171128

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/786

CPC classification number: H01L29/42376 ,  H01L27/088 ,  H01L29/404 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.