公开(公告)号：US11594528B2

公开(公告)日：2023-02-28

申请号：US17330678

申请日：2021-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Wen Cho ,  Fu-Jye Liang ,  Chun-Kuang Chen ,  Chih-Tsung Shih ,  Li-Jui Chen ,  Po-Chung Cheng ,  Chin-Hsiang Lin

IPC: H01L27/02 ,  G03F1/36 ,  G06F30/30 ,  G06F30/39 ,  G06F30/20 ,  G06F119/18

Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.

公开(公告)号：US11437161B1

公开(公告)日：2022-09-06

申请号：US17243300

申请日：2021-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Lin Chang ,  Chieh Hsieh ,  Shang-Chieh Chien ,  Han-Lung Chang ,  Heng-Hsin Liu ,  Li-Jui Chen ,  Chin-Hsiang Lin

IPC: G21K1/06 ,  G03F7/20 ,  H05G2/00

Abstract: An apparatus includes an extreme ultraviolet light source vessel having an intermediate focus, a scanner having a light source aperture, and a deflection module arranged between the intermediate focus and the light source aperture. The deflection module includes a first electrode plate and a second electrode plate, configured to create an electric field therebetween. Tin particles moving from the intermediate focus to the light source aperture passes through the deflection module, and are deflected by the electric field therein.

公开(公告)号：US11162777B2

公开(公告)日：2021-11-02

申请号：US16725222

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Hsiang Tseng ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Jui-Chun Peng ,  Ho-Ping Chen

IPC: G01B11/02 ,  H01L23/544 ,  G03F9/00

Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

公开(公告)号：US10510580B2

公开(公告)日：2019-12-17

申请号：US16103988

申请日：2018-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US20180151738A1

公开(公告)日：2018-05-31

申请号：US15455603

申请日：2017-03-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/66 ,  H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76843 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/66545 ,  H01L29/66795

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US09899496B2

公开(公告)日：2018-02-20

申请号：US14688120

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sey-Ping Sun ,  Sung-Li Wang ,  Chin-Hsiang Lin ,  Neng-Kuo Chen ,  Clement Hsingjen Wann

IPC: H01L21/425 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L21/324 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/785

Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.

公开(公告)号：US09698065B2

公开(公告)日：2017-07-04

申请号：US14873480

申请日：2015-10-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Tien Chang ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: H01L21/00 ,  H01L21/26 ,  F27B17/00 ,  H01L21/66 ,  H01L21/67 ,  H05B1/02 ,  H01L21/324

CPC classification number: H01L22/26 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/67248 ,  H05B1/0233

Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.

公开(公告)号：US20170140942A1

公开(公告)日：2017-05-18

申请号：US15419943

申请日：2017-01-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Chi-Yuan Shih ,  Gin-Chen Huang ,  Clement Hsingjen Wann ,  Li-Chi Yu ,  Chin-Hsiang Lin ,  Ling-Yen Yeh ,  Meng-Chun Chang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Ta-Chun Ma ,  Yen-Chun Huang

IPC: H01L21/285 ,  H01L27/088 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L21/28518 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

公开(公告)号：US20160274463A1

公开(公告)日：2016-09-22

申请号：US14658354

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Han Lai ,  Ching-Yu Chang ,  Cheng-Han Wu ,  Siao-Shan Wang ,  Chin-Hsiang Lin

IPC: G03F7/32 ,  G03F7/40 ,  G03F7/38 ,  G03F7/16 ,  G03F7/20

CPC classification number: G03F7/325 ,  G03F7/0382 ,  G03F7/38 ,  G03F7/40

Abstract: A material layer is formed over a substrate. A negative tone photoresist layer is formed over the material layer. An exposure process is performed to the negative tone photoresist layer. A post-exposure bake (PEB) process is performed to the negative tone photoresist layer. After the exposure process and the PEB process, the negative tone photoresist layer is treated with a solvent. The solvent contains a chemical having a greater dipole moment than n-butyl acetate (n-BA).

Abstract translation: 在衬底上形成材料层。 在材料层上形成负色调光致抗蚀剂层。 对负色调光致抗蚀剂层进行曝光处理。 对负色光致抗蚀剂层进行后曝光烘焙（PEB）处理。 在曝光处理和PEB处理之后，用溶剂处理负色调光致抗蚀剂层。 溶剂含有比乙酸正丁酯（n-BA）具有更大的偶极矩的化学物质。

公开(公告)号：US09425286B2

公开(公告)日：2016-08-23

申请号：US14152400

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Jeff J. Xu ,  Pang-Yen Tsai

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7849

Abstract: Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.

Abstract translation: 公开了可以增强载流子迁移率的各种源极/漏极应力源及其制造方法。 示例性源极/漏极应力器包括设置在第二材料的衬底上的第一材料的种子层，第一材料不同于第二材料; 设置在种子层上的松弛外延层; 以及设置在松弛外延层上的外延层。