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    DIELECTRIC SEPARATION OF PARTIAL GAA FETS
    51.
    发明申请
    DIELECTRIC SEPARATION OF PARTIAL GAA FETS 审中-公开

    公开(公告)号：US20190181140A1

    公开(公告)日：2019-06-13

    申请号：US15977949

    申请日：2018-05-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Palle ,  Rwik Sengupta ,  Mohammad Ali Pourghaderi

    IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

    Abstract: A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.

    Multiple channel length finFETs with same physical gate length
    57.
    发明授权
    Multiple channel length finFETs with same physical gate length 有权
    具有相同物理栅极长度的多通道长度finFET

    公开(公告)号：US09466669B2

    公开(公告)日：2016-10-11

    申请号：US14683926

    申请日：2015-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mark S. Rodder ,  Borna Obradovic ,  Rwik Sengupta

    IPC: H01L29/66 ,  H01L21/3205 ,  H01L27/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

    CPC classification number: H01L29/10 ,  H01L21/0257 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/423 ,  H01L29/42376

    Abstract: A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.

    Abstract translation: 半导体结构包括第一鳍式FET器件，其包括第一鳍片，侧壁上的第一栅极电极结构和第一鳍片的上表面，第一栅电极结构下方的第一沟道区域，第一鳍片中的第一源极和漏极区域 在第一沟道区域的相对侧上，以及第二鳍状FET器件，其包括第二鳍片，侧壁上的第二栅电极结构和第二鳍片的上表面，第二栅电极结构下方的第二沟道区域，以及第二源极和 第二鳍片的漏极区域在第二沟道区域的相对侧上。 第二栅极电极结构具有与第一栅极电极结构的第一物理栅极长度基本相同的第二物理栅极长度，并且第二finFET器件具有与第一栅极电极结构的第一有效沟道长度不同的第二有效沟道长度 第一栅电极结构。

    Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same
    58.
    发明授权
    Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same 有权
    包括finFET和局部互连层的半导体器件及其制造方法

    公开(公告)号：US09443851B2

    公开(公告)日：2016-09-13

    申请号：US14534536

    申请日：2014-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rwik Sengupta ,  Raheel Azmat

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768

    CPC classification number: H01L27/0886 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a finFET, a metal routing layer, a first local interconnect layer, and a second local interconnect layer. The finFET may include a channel, a first source/drain region, a second source/drain region, and a gate stack. The metal routing layer may be separated from the finFET in a vertical direction. The first local interconnect layer may include a first local interconnect that contacts a first metal route in the metal routing layer and that electrically connects to the first source/drain region. The second local interconnect layer may include a second local interconnect that contacts a second metal route in the metal routing layer and that electrically connects to the gate stack.

    Abstract translation: 提供了半导体器件及其形成方法。 半导体器件可以包括finFET，金属布线层，第一局部互连层和第二局部互连层。 finFET可以包括沟道，第一源极/漏极区域，第二源极/漏极区域和栅极堆叠。 金属布线层可以在垂直方向上与finFET分离。 第一局部互连层可以包括接触金属布线层中的第一金属路径并且电连接到第一源极/漏极区的第一局部互连。 第二局部互连层可以包括接触金属布线层中的第二金属路径并且电连接到栅极堆叠的第二局部互连。

    Flip-flop layout architecture implementation for semiconductor device
    59.
    发明授权
    Flip-flop layout architecture implementation for semiconductor device 有权
    半导体器件的触发器布局架构实现

    公开(公告)号：US09324715B2

    公开(公告)日：2016-04-26

    申请号：US14504075

    申请日：2014-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun

    IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207

    Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

    Abstract translation: 半导体器件包括包括PMOSFET和NMOSFET区域的衬底。 第一和第二栅电极设置在PMOSFET区上，第三和第四栅电极设置在NMOSFET区上。 提供连接触点以连接第二栅电极和第三栅电极，并且连接线设置在连接触头上以与连接触头交叉，并将第一栅电极连接到第四栅电极。

    NANOSHEET FETS WITH STACKED NANOSHEETS HAVING SMALLER HORIZONTAL SPACING THAN VERTICAL SPACING FOR LARGE EFFECTIVE WIDTH
    60.
    发明申请
    NANOSHEET FETS WITH STACKED NANOSHEETS HAVING SMALLER HORIZONTAL SPACING THAN VERTICAL SPACING FOR LARGE EFFECTIVE WIDTH 有权
    具有小型水平间隔的堆叠纳米结构的纳米结构FET与大幅有效宽度的垂直间距

    公开(公告)号：US20150364546A1

    公开(公告)日：2015-12-17

    申请号：US14722402

    申请日：2015-05-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Rwik Sengupta

    IPC: H01L29/10 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/775

    Abstract: A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.

    Abstract translation: 包括堆叠的纳米片场效应晶体管（FET）的器件可以包括衬底，衬底上的第一沟道图案，第一沟道图案上的第二沟道图案，被配置为围绕第一沟道图案的部分的栅极和部分 的第二沟道图案和第一沟道图案和第二沟道图案的相对端上的源极/漏极区域。 第一和第二通道图案可以各自包括布置在平行于基板的表面的相应水平平面中的相应的多个纳米片。 纳米片可以在相邻的纳米片之间的水平间隔距离处彼此间隔开。 第二通道图案可以与第一通道图案间隔开距离第一通道图案到第二通道图案的垂直间隔距离大于水平间隔距离。

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