公开(公告)号：US09373387B1

公开(公告)日：2016-06-21

申请号：US14659937

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/417 ,  G06F17/50 ,  G11C11/412

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

公开(公告)号：US20160142054A1

公开(公告)日：2016-05-19

申请号：US14639755

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3296 ,  G06F17/505 ,  G06F2209/5019 ,  G06F2217/68 ,  G06F2217/78 ,  H03K19/018507 ,  Y02D10/172 ,  Y02D10/174

Abstract: A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication.

Abstract translation: 一种用于缩放提供给片上系统（SOC）的不同模块的电压的方法包括在SOC的能量性能引擎处接收SOC的第一模块的使用历史的第一指示，以及SOC的第一指示 SOC的第二个模块的使用历史。 该方法包括接收指示SOC的电池的剩余电池寿命的电池寿命指示。 该方法还包括基于第一指示，第二指示和电池寿命指示来调整提供给SOC的第一模块的第一电源电压。 该方法还包括基于第一指示，第二指示和电池寿命指示来调整提供给SOC的第二模块的第二电源电压。

公开(公告)号：US09165929B2

公开(公告)日：2015-10-20

申请号：US14322207

申请日：2014-07-02

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161

Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.

Abstract translation: 互补翅片场效应晶体管（FinFET）包括具有p沟道鳍片的p型器件。 p沟道鳍可以包括相对于半导体衬底而晶格失配的第一材料。 第一种材料可能具有压缩应变。 FinFET器件还包括具有再通道鳍片的n型器件。 n沟道翅片可以包括具有相对于半导体衬底的晶格失配的拉伸应变的第二材料。 p型器件和n型器件配合形成互补FinFET器件。

公开(公告)号：US09153587B2

公开(公告)日：2015-10-06

申请号：US14659893

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265 ,  G06F17/50

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region. The first region has a first doping concentration greater than a second doping concentration of the second region. The first fin-type conduction channel comprises first ion implants implanted into the substrate at a first depth and second ion implants implanted into the substrate at a different depth. The third region has a third doping concentration, and the fourth region has a fourth doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括用于提供具有第一和第二区域的第一鳍式传导沟道的装置，用于提供具有在第三区域上方的第四区域的第二鳍式传导沟道的装置，以及用于屏蔽漏电耦合到 第一区域和第三区域中的至少一个。 第一区域具有大于第二区域的第二掺杂浓度的第一掺杂浓度。 第一鳍型传导通道包括在第一深度处植入衬底中的第一离子植入物和在不同深度处植入衬底中的第二离子植入物。 第三区域具有第三掺杂浓度，第四区域具有第四掺杂浓度。

公开(公告)号：US20150270134A1

公开(公告)日：2015-09-24

申请号：US14284958

申请日：2014-05-22

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/285 ,  H01L29/66 ,  C23C14/54 ,  C23C16/52 ,  C23C16/46 ,  C23C14/24 ,  H01L21/324 ,  H01L29/45

CPC classification number: H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

Abstract translation: 一种方法包括通过化学气相沉积（CVD）在n型金属氧化物半导体（NMOS）器件的源极/漏极区域和p型MOS（PMOS）器件的源极/漏极区域上形成第一金属层， 或非能量物理气相沉积（PVD）。 该方法还包括在形成第一金属层之后在第一金属层上选择性地执行快速热退火（RTA）工艺。

公开(公告)号：US20150262875A1

公开(公告)日：2015-09-17

申请号：US14471086

申请日：2014-08-28

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76879 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76885

Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.

Abstract translation: 一种方法包括形成包括衬底，氧化物层和第一低k层的电子器件结构。 该方法还包括通过图案化氧化物层来形成开口，用导电材料填充开口以在开口内形成导电结构，以及使用第一低k层作为蚀刻停止层去除氧化物层。 导电结构接触第一低k层。 去除氧化物层包括相对于氧化物层执行化学气相蚀刻工艺以形成蚀刻副产物并除去蚀刻副产物。 该方法包括使用使第二低k层限定一个或多个空腔的沉积工艺形成第二低k层。 每个空腔限定在第一导电结构和相邻的导电结构之间，第一和第二导电结构之间具有小于阈值距离的间隔。

公开(公告)号：US08799847B1

公开(公告)日：2014-08-05

申请号：US13838462

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  H01L29/66795

Abstract: Methods for designing fin-based field effect transistors (FinFETs) are disclosed. In one embodiment, an initial FinFET design is evaluated to ascertain the space between fins (i.e., the “fin pitch”). Additionally, the spacing between interconnect metal modules (i.e., the “metal pitch”) is ascertained. A ratio of metal pitch to fin pitch is established. From this initial ratio, isotropically scaled sizes are considered along with anisotropically scaled sizes. The variously scaled sizes are compared to design criteria to see what new size best fits the design criteria.

Abstract translation: 公开了用于设计基于鳍的场效应晶体管（FinFET）的方法。 在一个实施例中，评估初始FinFET设计以确定翅片之间的空间（即，“翅片间距”）。 此外，确定互连金属模块之间的间隔（即，“金属间距”）。 确定了金属间距与翅片间距的比率。 从这个初始比例来看，各向异性缩放的尺寸以及各向异性尺寸的尺寸被考虑。 将不同尺寸的尺寸与设计标准进行比较，以了解最符合设计标准的新尺寸。

公开(公告)号：US11973019B2

公开(公告)日：2024-04-30

申请号：US17324614

申请日：2021-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L28/40 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16146

Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.

公开(公告)号：US20230299048A1

公开(公告)日：2023-09-21

申请号：US17655394

申请日：2022-03-18

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Stanley Seungchul Song ,  Lily Zhao

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06586 ,  H01L2225/06541 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L24/14

Abstract: A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

公开(公告)号：US11310911B2

公开(公告)日：2022-04-19

申请号：US16929004

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jonghae Kim ,  Periannan Chidambaram

IPC: H05K1/11 ,  G06F1/18 ,  H05K3/10 ,  H05K3/40 ,  H05K1/02

Abstract: An integrated circuit (IC) package is described. The IC package includes a metallization structure. The IC package also includes a first die in a package substrate layer. The package substrate includes a first surface and a second surface, opposite the first surface. The second surface of the package substrate layer is on the metallization structure. The IC package further includes a second die on the first surface of the package substrate layer and on the first die. The IC package also includes through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure. The IC package further includes package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.