公开(公告)号：US20050287735A1

公开(公告)日：2005-12-29

申请号：US11202032

申请日：2005-08-12

Applicant: Takashi Nakagawa ,  Takashi Hase

Inventor： Takashi Nakagawa ,  Takashi Hase

IPC: C23C16/30 ,  H01L21/00 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76

CPC classification number: H01L28/55 ,  H01L28/65

Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.

公开(公告)号：US20050285276A1

公开(公告)日：2005-12-29

申请号：US11147038

申请日：2005-06-07

Applicant: Akihito Matsumoto ,  Toshiyuki Kamiya

Inventor： Akihito Matsumoto ,  Toshiyuki Kamiya

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L23/48 ,  H01L27/10 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01L21/76895 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/60

Abstract: A capacitor section is formed with a lower electrode provided on a SiO2 layer above an impurity layer provided in a substrate, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer. Further, the semiconductor device is equipped with a SiO2 layer that electrically insulates the upper electrode from a wiring, a first contact hole in which a W plug is formed for electrically connecting the impurity layer and the lower electrode, and a second contact hole for electrically connecting the upper electrode and the wiring. The first contact hole and the second contact hole are opened at positions mutually deviated as viewed in a plan view of the capacitor section.

Abstract translation: 电容器部分形成有设置在设置在基板中的杂质层上方的SiO 2层上的下电极，设置在下电极上的铁电层和设置在铁电层上的上电极。 此外，半导体器件配备有将上部电极与布线电绝缘的SiO 2层，形成有用于将杂质层和下部电极电连接的W型插塞的第一接触孔 以及用于电连接上电极和布线的第二接触孔。 第一接触孔和第二接触孔在电容器部分的俯视图中观察到的相互偏离的位置开口。

公开(公告)号：US20050285219A1

公开(公告)日：2005-12-29

申请号：US11216147

申请日：2005-09-01

Applicant: Eiji Sakagami

Inventor： Eiji Sakagami

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/10 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00 ,  H01L21/335

CPC classification number: H01L21/28202 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A charge storage layer (112) in a gate insulating film of a cell transistor is so formed as not to extend from a channel region of a cell to an element isolation region. Since no electric charge moves from the charge storage layer (112) on the channel onto the element isolation region, the charge retention characteristics improves. Unlike a gate insulating film of a cell transistor, a gate insulating film of a selection transistor is formed without including the charge storage layer (112). This stabilizes read operation because the threshold value of the transistor does not vary. Of peripheral transistors, a thick gate oxide film is formed for a transistor requiring a high-breakdown-voltage gate oxide film, and a thin gate oxide film is formed for a transistor requiring high drivability. This realizes a high operating speed.

Abstract translation: 电池晶体管的栅极绝缘膜中的电荷存储层（112）形成为不从单元的沟道区延伸到元件隔离区。 由于没有电荷从沟道上的电荷存储层（112）移动到元件隔离区上，所以电荷保持特性提高。 与单元晶体管的栅极绝缘膜不同，形成选择晶体管的栅极绝缘膜，而不包括电荷存储层（112）。 这使得读取操作稳定，因为晶体管的阈值不变。 在外围晶体管中，形成了要求高耐压栅氧化膜的晶体管的厚栅氧化膜，并且形成了要求高驱动能力的晶体管的薄栅氧化膜。 这实现了高的运行速度。

公开(公告)号：US20050285182A1

公开(公告)日：2005-12-29

申请号：US11197803

申请日：2005-08-05

Applicant: Franz Schuler

Inventor： Franz Schuler

IPC: H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885 ,  H01L29/792

Abstract: A memory cell, memory cell arrangement, and method for producing a memory cell arrangement is described where electric charge carriers can be introduced from a trench structure, which delivers charge carriers, into a charge storage area by applying a predefined electrical potential to the cell. The memory cell provides for programming with a reduced energy requirement

Abstract translation: 描述了一种用于产生存储单元布置的存储单元，存储单元布置和方法，其中可以通过向单元施加预定的电位，从电荷载流子的沟槽结构引入电荷载流子。 存储单元提供了减少能量需求的编程

公开(公告)号：US20050285173A1

公开(公告)日：2005-12-29

申请号：US11051643

申请日：2005-01-27

Applicant: Kouichi Nagai ,  Hideaki Kikuchi ,  Naoya Sashida ,  Yasutaka Ozaki

Inventor： Kouichi Nagai ,  Hideaki Kikuchi ,  Naoya Sashida ,  Yasutaka Ozaki

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8246 ,  H01L23/48 ,  H01L23/52 ,  H01L27/06 ,  H01L27/108 ,  H01L27/115 ,  H01L29/40 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/11502 ,  H01L21/02063 ,  H01L27/0688 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/57

Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected to the second conductor plug 62 or the third conductor plug 62.

Abstract translation: 半导体器件包括形成在半导体衬底10上的第一绝缘膜26，埋在第一接触孔28a中的第一导体插塞32，其形成在源极/漏极扩散层22上，形成在第一绝缘膜26上的电容器44， 形成在第一绝缘膜26上的覆盖电容器44的第一氢扩散防止膜48，形成在第一氢扩散防止膜上并具有表面平坦化的第二绝缘膜50，形成在第一绝缘膜52上的第二防止氢扩散膜52 表面被平坦化的氢扩散防止膜26，形成在第二绝缘膜50上的第二氢扩散防止膜52，埋在第二接触孔56中的第二导体插塞62，第二接触孔56形成在下电极38或上电极42 电容器44，埋在第一接线孔58中的第三导体插头62，并形成在第一导体插头32上 连接64连接到第二导体插头62或第三导体插头62。

公开(公告)号：US20050285170A1

公开(公告)日：2005-12-29

申请号：US11101645

申请日：2005-04-08

Applicant: Takumi Mikawa ,  Yuji Judai

Inventor： Takumi Mikawa ,  Yuji Judai

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76

CPC classification number: H01L27/11502 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/90

Abstract: A semiconductor device includes: first and second conductive layers; a first insulating film; a first plug; a second insulating film; a first opening; and a capacitor constituted by a lower electrode made of a first metal film formed on the wall and bottom of the first opening and electrically connected to the upper end of the first plug, a capacitive dielectric film made of a ferroelectric film formed on the lower electrode, and an upper electrode made of a second metal film formed on the capacitive dielectric film. The second conductive layer and the upper electrode are electrically connected to each other in the first and second insulating films.

Abstract translation: 半导体器件包括：第一和第二导电层; 第一绝缘膜; 第一个插头 第二绝缘膜; 第一个开口 以及电容器，其由形成在所述第一开口的壁和所述第一开口的底部上的由第一金属膜制成的下电极构成，并且电连接到所述第一插塞的上端;电容电介质膜，其由在所述下电极上形成的铁电体膜 以及由形成在电容绝缘膜上的第二金属膜构成的上电极。 第二导电层和上电极在第一和第二绝缘膜中彼此电连接。

公开(公告)号：US20050282379A1

公开(公告)日：2005-12-22

申请号：US11149267

申请日：2005-06-10

Applicant: Yoshiaki Saito ,  Hideyuki Sugiyama

Inventor： Yoshiaki Saito ,  Hideyuki Sugiyama

IPC: G11C11/16 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/8246 ,  H01L27/01 ,  H01L27/12 ,  H01L27/22 ,  H01L29/66 ,  H01L29/82 ,  H01L31/0392

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  H01L29/66984 ,  Y10S977/932 ,  Y10S977/933 ,  Y10S977/936

Abstract: A spin transistor includes a first conductive layer that is made of a ferromagnetic material magnetized in a first direction, and functions as one of a source and a drain; a second conductive layer that is made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction, and functions as the other one of the source and the drain. The spin transistor also includes a channel region that is located between the first conductive layer and the second conductive layer, and introduces electron spin between the first conductive layer and the second conductive layer; a gate electrode that is located above the channel region; and a tunnel barrier film that is located between the channel region and at least one of the first conductive layer and the second conductive layer.

Abstract translation: 自旋晶体管包括由沿第一方向磁化的铁磁材料制成的第一导电层，并且用作源极和漏极之一; 第二导电层，其由在相对于第一方向反平行的第一方向和第二方向中的一个中被磁化的铁磁材料制成，并且用作源极和漏极中的另一个。 自旋晶体管还包括位于第一导电层和第二导电层之间的沟道区，并且在第一导电层和第二导电层之间引入电子自旋; 位于通道区域上方的栅电极; 以及位于所述沟道区域和所述第一导电层和所述第二导电层中的至少一个之间的隧道势垒膜。

公开(公告)号：US06977209B2

公开(公告)日：2005-12-20

申请号：US10931905

申请日：2004-09-01

Applicant: Teiichiro Nishizaka

Inventor： Teiichiro Nishizaka

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/20 ,  H01L21/302

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/7923 ,  Y10S257/909

Abstract: A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third storage node provided on the substrate and a third gate electrode provided on the third storage node. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided. A storage node, Node 1, of interest, with the control gate channel as a drain, is read without the intermediary of the second node, which is not of interest, such that reading of Node1 unaffected by the second node.

Abstract translation: 2位单元由设置在基板表面上的第一和第二扩散区域，与第一和第二扩散区域相邻的第一和第二存储节点，设置在第一和第二存储节点上的第一和第二栅极电极，第三存储器 节点，设置在第三存储节点上的第三栅电极。 第一和第二栅极共同连接以形成字线电极。 提供了与字线电极成直角的控制栅极电极和设置在控制栅电极的纵向端的衬底表面中的第三扩散区域。 在不具有不感兴趣的第二节点的情况下读取感兴趣的具有控制门信道作为漏极的存储节点，节点1，使得节点1的读取不受第二节点的影响。

公开(公告)号：US20050276106A1

公开(公告)日：2005-12-15

申请号：US10869475

申请日：2004-06-15

Applicant: Chiou-Feng Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC: G11C11/34 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568

Abstract: NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

Abstract translation: NAND闪速存储单元阵列具有控制栅极和电荷存储门，它们成对地排列成位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。 每个堆叠对中的栅极彼此自对准，并且电荷存储栅极是氮化物或氮化物和氧化物的组合。 通过从硅衬底到电荷存储门的热电子注入来完成编程，以在电荷存储门中建立负电荷。 通过从电荷存储栅极到硅衬底的沟道隧穿或通过从硅衬底到电荷存储栅的热空穴注入来完成擦除。 该阵列被偏置，使得所有的存储单元可以同时被擦除，而编程是位可选择的。

公开(公告)号：US06975534B2

公开(公告)日：2005-12-13

申请号：US10615379

申请日：2003-07-09

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: G11C11/15 ,  G11C11/14 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C5/025 ,  B82Y10/00 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/228

Abstract: Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array.

Abstract translation: 对应于相应的MTJ（磁隧道结）存储单元行提供读字线和写字线，并且对应于相应的MTJ存储单元列提供位线和参考电压线。 相邻的MTJ存储器单元共享这些信号线中的至少一个。 结果，可以扩大设置在整个存储器阵列中的信号线的间距。 因此，可以有效地布置MTJ存储器单元，实现存储器阵列的改进的集成。