公开(公告)号：US20100157687A1

公开(公告)日：2010-06-24

申请号：US12645337

申请日：2009-12-22

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

IPC: G11C16/06 ,  G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与之绝缘。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US20060068529A1

公开(公告)日：2006-03-30

申请号：US11281182

申请日：2005-11-16

Applicant: Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC: H01L21/8232

CPC classification number: G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

公开(公告)号：US20050145923A1

公开(公告)日：2005-07-07

申请号：US10753103

申请日：2004-01-06

Applicant: Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

Inventor： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC: G11C16/04 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: NAND flash memory cell array and fabrication process in which control gates and floating gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other and

Abstract translation: NAND闪速存储器单元阵列和制造工艺，其中控制栅极和浮置栅极成对地堆叠成排列在位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。 每个堆叠对中的门彼此自对齐，并且时，文本丢失或难以辨认

公开(公告)号：US06654291B2

公开(公告)日：2003-11-25

申请号：US10155953

申请日：2002-05-24

Applicant: Shang Tarng Jan ,  Der-Tsyr Fan

Inventor： Shang Tarng Jan ,  Der-Tsyr Fan

IPC: G11C1604

CPC classification number: G11C16/14 ,  G11C16/24

Abstract: Embodiments of the present invention are directed to an improved EEPROM (electrically erasable programmable read-only memory) in which the memory cells can be selectively erased. The EEPROM comprises a first memory cell having a first control gate and a first source, and a second memory cell having second control gate and a second source. If the first and second control gates are configured to receive a control gate voltage, the first source is configured to receive a first source voltage, and the second source is configured to receive a second source voltage different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells. If the first and second sources are configured to receive a source voltage, the first control gate is configured to receive a first control gate voltage, and the second control gate is configured to receive a second control gate voltage different from the first control gate voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.

Abstract translation: 本发明的实施例涉及可以选择性地擦除存储器单元的改进的EEPROM（电可擦除可编程只读存储器）。 EEPROM包括具有第一控制栅极和第一源极的第一存储单元，以及具有第二控制栅极和第二源极的第二存储单元。 如果第一和第二控制栅极被配置为接收控制栅极电压，则第一源被配置为接收第一源极电压，并且第二源被配置为接收不同于第一源极电压的第二源极电压，以便擦除 第一和第二存储器单元之一并且保存第一和第二存储器单元中的另一个。 如果第一和第二源被配置为接收源电压，则第一控制栅极被配置为接收第一控制栅极电压，并且第二控制栅极被配置为接收不同于第一控制栅极电压的第二控制栅极电压，从而 以便擦除第一和第二存储器单元之一并保存第一和第二存储器单元中的另一个。

公开(公告)号：US06380072B2

公开(公告)日：2002-04-30

申请号：US09725602

申请日：2000-11-29

Applicant: John Chu ,  Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

Inventor： John Chu ,  Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

IPC: H01L214763

CPC classification number: H01L21/02

Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a). providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectric layer on the conductive layer, d) forming a titanium nitride layer directly on the dielectric layer without contacting the conductive layer, and e) patternizing the titanium nitride layer, the dielectric layer and the conductive layer, wherein the dielectric layer is used for avoiding spontaneous electrochemical reaction between the titanium nitride layer and the conductive layer,

Abstract translation: 提供了一种制造具有优异金属化的半导体器件的方法。 该方法包括以下步骤：a）。 提供半导体衬底，b）在所述半导体衬底上形成导电层，c）在所述导电层上形成电介质层，d）直接在所述电介质层上形成氮化钛层而不与所述导电层接触，e）使 氮化钛层，电介质层和导电层，其中介电层用于避免氮化钛层和导电层之间的自发电化学反应，

公开(公告)号：US5926715A

公开(公告)日：1999-07-20

申请号：US868427

申请日：1997-06-04

Applicant: Der-Tsyr Fan ,  Liang-Choo Hsia ,  Jr-Min Tsaur

Inventor： Der-Tsyr Fan ,  Liang-Choo Hsia ,  Jr-Min Tsaur

IPC: H01L21/225 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/2255

Abstract: A method of forming a LDD fabrication by automatic phosphoric silicate glass (PSG) doping is disclosed herein. A phosphoric silicate glass serves as a diffusion source. The phosphorous ions of phosphoric silicate glass can be driven into a substrate to form a lightly-doped drain (LDD)by a high temperature during a thermal annealing process. The diffusion method can prevent from the damage in the substrate and the increasing of leakage current. Additionally, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from sequentially diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can effectively control the impurity concentration of the lightly-doped drain (LDD) to prevent from the impurity concentration of the LDD over high.

Abstract translation: 本文公开了通过自动磷酸硅酸盐玻璃（PSG）掺杂形成LDD制造的方法。 磷酸硅玻璃用作扩散源。 磷酸硅酸盐玻璃的磷离子可以被驱动到衬底中，以在热退火过程中通过高温形成轻掺杂漏极（LDD）。 扩散方法可以防止衬底的损坏和漏电流的增加。 另外，通过热氧化工艺在栅电极和衬底的表面上形成热氧化层。 在随后的热处理过程中，热氧化物层可以防止离子顺序地扩散到衬底中。 因此，本发明可以有效地控制轻掺杂漏极（LDD）的杂质浓度，以防止LDD的杂质浓度过高。

公开(公告)号：US07974136B2

公开(公告)日：2011-07-05

申请号：US12645337

申请日：2009-12-22

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

IPC: G11C16/04

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US20070257299A1

公开(公告)日：2007-11-08

申请号：US11381948

申请日：2006-05-05

Applicant: Bomy Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

Inventor： Bomy Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC: H01L29/788

CPC classification number: H01L29/7885 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328

Abstract: Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates. In another embodiment, the conductors adjacent to the bit line diffusions are program lines, and the third conductors are word lines which extend in a direction perpendicular to the program lines and the diffusions.

Abstract translation: 半导体存储器阵列及其制造方法，其中在衬底中形成多个位线扩散，以及在位线扩散之间成对形成的存储单元，其中每对单元具有与位线相邻的第一和第二导体 在第一和第二导体旁边的扩散，浮置栅极，浮置栅极之间的擦除栅极以及在擦除栅极下方的衬底中的源极线扩散以及电容耦合到浮动栅极的至少一个附加导体。 在一些公开的实施例中，与位线扩散相邻的导体是字线，并且附加导体由耦合到相应浮动栅极的一对耦合栅极或耦合到两个 浮动门。 在另一个实施例中，与位线扩散相邻的导体是编程线，并且第三导体是在垂直于编程线和扩散的方向上延伸的字线。

公开(公告)号：US5747378A

公开(公告)日：1998-05-05

申请号：US863402

申请日：1997-05-27

Applicant: Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting-S. Wang

Inventor： Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting-S. Wang

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/22

CPC classification number: H01L27/10873 ,  H01L21/2255 ,  H01L21/823418 ,  H01L29/6656 ,  H01L29/66575 ,  Y10S148/144

Abstract: A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.

Abstract translation: 本文公开了一种用于形成动态随机存取存储器单元的无损耗掺杂的方法。 磷酸硅玻璃作为扩散源沉积。 在热退火过程中，磷酸硅玻璃的磷离子可以扩散到衬底中，以通过高温形成源/漏区。 接下来，通过热氧化工艺在栅电极和衬底的表面上形成热氧化层。 在随后的热处理过程中，热氧化物层可以防止离子扩散到衬底中。 因此，本发明可以减少动态随机存取存储器的损坏。

公开(公告)号：US07217621B2

公开(公告)日：2007-05-15

申请号：US11281182

申请日：2005-11-16

Applicant: Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC: H01L21/336

CPC classification number: G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Abstract translation: 自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。 每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位 排列源扩散。 擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合 其他大门。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。