公开(公告)号：US5747378A

公开(公告)日：1998-05-05

申请号：US863402

申请日：1997-05-27

Applicant: Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting-S. Wang

Inventor： Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting-S. Wang

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/22

CPC classification number: H01L27/10873 ,  H01L21/2255 ,  H01L21/823418 ,  H01L29/6656 ,  H01L29/66575 ,  Y10S148/144

Abstract: A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.

Abstract translation: 本文公开了一种用于形成动态随机存取存储器单元的无损耗掺杂的方法。 磷酸硅玻璃作为扩散源沉积。 在热退火过程中，磷酸硅玻璃的磷离子可以扩散到衬底中，以通过高温形成源/漏区。 接下来，通过热氧化工艺在栅电极和衬底的表面上形成热氧化层。 在随后的热处理过程中，热氧化物层可以防止离子扩散到衬底中。 因此，本发明可以减少动态随机存取存储器的损坏。

公开(公告)号：US06812148B2

公开(公告)日：2004-11-02

申请号：US10219094

申请日：2002-08-13

Applicant: Chieh-Ju Chang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Yifu Chung

Inventor： Chieh-Ju Chang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Yifu Chung

IPC: H01L21311

CPC classification number: H01L21/28238 ,  C23C8/02 ,  C23C8/10 ,  C23C8/80 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/7621 ,  H01L29/518

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.

Abstract translation: 本发明的实施例涉及一种用于在凹槽LOCOS工艺中防止栅极氧化物稀化的方法。 多个沟槽由图案化的衬垫氧化物和图案化的氮化硅层分离。去除图案化的氮化硅层和图案化衬垫氧化物层，以暴露衬底的表面作为半导体器件的有效区域。 在衬底上的有源区域中的离子驱动通过在预定温度和足够量的氧气下引导氧和氮流向衬底来进行，以至少基本上防止在场氧化物区域上形成氮化硅 。 该方法还包括在有源区上形成牺牲氧化物层，去除牺牲氧化物层以暴露有源区，以及在有源区上形成栅极氧化物层。

公开(公告)号：US06245608B1

公开(公告)日：2001-06-12

申请号：US09332125

申请日：1999-06-14

Applicant: Tsai-Sen Lin ,  Chon-Shin Jou ,  Der-Tsyr Fan

Inventor： Tsai-Sen Lin ,  Chon-Shin Jou ,  Der-Tsyr Fan

IPC: H01L218238

CPC classification number: H01L21/28512 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823871 ,  Y10S438/919

Abstract: A method of contact ion implantation is disclosed. Only one mask and a dosage-enhanced implantation is utilized to form different types of doped contact regions. A blanket ion implantation is first carried out, and all the contact regions of first and second type are formed with the first conductive type impurities. Then a mask is defined to cover the first type contact regions and expose the second type regions. A second ion implantation is now carried out to implant impurity ions of second conductive type into the second type contact regions. The dosage of these second conductive type ions is determined so that, the second type contact regions are convert from the first conductive type into section conductive type.

Abstract translation: 公开了接触离子注入的方法。 仅使用一个掩模和剂量增强的注入来形成不同类型的掺杂接触区域。 首先进行覆盖式离子注入，并且第一和第二类型的所有接触区域由第一导电类型的杂质形成。 然后，限定掩模以覆盖第一类型接触区域并暴露第二类型区域。 现在执行第二离子注入以将第二导电类型的杂质离子注入到第二类型接触区域中。 确定这些第二导电型离子的剂量使得第二类型的接触区域从第一导电类型转换为导电型。

公开(公告)号：US5882984A

公开(公告)日：1999-03-16

申请号：US728305

申请日：1996-10-09

Applicant: Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

Inventor： Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

IPC: H01L21/762 ,  H01L21/8242 ,  H01L21/76

CPC classification number: H01L27/10844 ,  H01L21/76202

Abstract: The present invention is a method for increasing the refresh time of DRAM. This invention is for decreasing the stress between the bird's beak of field oxide and silicon substrate by using fluorine ion implant before field oxidation and the optimal structure of LOCOS to effectively preventing the current leakage from the bird's beak of field oxide. Therefore, this invention can increase the refresh time of DRAM and greatly enhance the performance in DRAM.

Abstract translation: 本发明是增加DRAM刷新时间的方法。 本发明是通过在场氧化之前使用氟离子注入和LOCOS的最佳结构来减少场氧化物的鸟嘴和硅衬底之间的应力，以有效地防止来自场氧化物的鸟喙的电流泄漏。 因此，本发明可以增加DRAM的刷新时间并大大提高DRAM的性能。

公开(公告)号：US5837578A

公开(公告)日：1998-11-17

申请号：US895107

申请日：1997-07-16

Applicant: Der-Tsyr Fan ,  Jyh-Min Tsaur ,  Chon-Shin Jou ,  Tings Wang

Inventor： Der-Tsyr Fan ,  Jyh-Min Tsaur ,  Chon-Shin Jou ,  Tings Wang

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A trenched stack-capacitor applied in a memory unit is formed through a simple process of manufacturing a stack capacitor with high density. The process includes steps of: a) forming a contact window in the insulator for exposing a cell contact of the device; b) forming a first conducting layer over the insulator and on side-walls and a base of the contact window; c) forming an etching sacrificial layer over the first conducting layer and in the contact window; d) forming an etching masking layer over a portion of the etching sacrificial layer; e) forming a plural cylindrical etching sacrificial areas by removing an another portion of the etching sacrificial layer while retaining the etching sacrificial layer under the etching masking layer; f) forming a second conducting layer on the top of the etching masking layer, on side walls of the plural cylindrical etching sacrificial areas, over the first conducting layer and in the contact window; g) removing the plural cylindrical etching sacrificial areas while retaining the first conducting layer and the second conducting layer to form a first capacitor plate; h) forming a dielectric layer on the top of the first conducting layer and on the top and side walls of the second conducting layer; and i) forming a third conducting layer over the dielectric layer to serve as a second capacitor plate.

Abstract translation: 施加在存储器单元中的沟槽叠层电容器通过制造高密度堆叠电容器的简单工艺形成。 该方法包括以下步骤：a）在绝缘体中形成接触窗口，用于暴露设备的电池接触; b）在所述绝缘体上以及所述接触窗的侧壁和底座上形成第一导电层; c）在所述第一导电层上和所述接触窗中形成蚀刻牺牲层; d）在蚀刻牺牲层的一部分上形成蚀刻掩模层; e）通过去除蚀刻牺牲层的另一部分同时将蚀刻牺牲层保持在蚀刻掩模层下方而形成多个圆柱形蚀刻牺牲区域; f）在所述蚀刻掩模层的顶部，在所述多个圆柱形蚀刻牺牲区域的侧壁上，在所述第一导电层和所述接触窗口之上形成第二导电层; g）在保留第一导电层和第二导电层以形成第一电容器板的同时，去除多个圆柱形蚀刻牺牲区域; h）在第一导电层的顶部和第二导电层的顶壁和侧壁上形成电介质层; 以及i）在所述电介质层上形成第三导电层以用作第二电容器板。

公开(公告)号：US20060046207A1

公开(公告)日：2006-03-02

申请号：US11112454

申请日：2005-04-21

Applicant: Hsing Tsun Liu ,  Hsieh Hsin Huang ,  Chon-Shin Jou

Inventor： Hsing Tsun Liu ,  Hsieh Hsin Huang ,  Chon-Shin Jou

IPC: G03F7/38 ,  G03F7/40

CPC classification number: H01L21/6875

Abstract: Embodiments of the invention are directed to an exposure method for preventing wafer breakage, particularly of a trench-type power MOS device. In one embodiment, the exposure method includes: (a) providing a substrate; (b) forming a trench area and a non-trench area on the substrate; (c) carrying the substrate on a hot plate, the hot plate having a plurality of supporters corresponding to the non-trench area; and (d) performing photoresist coating and baking procedures to the substrate. The exposure method of the present invention can prevent wafer breakage due to rapid temperature variation so as to increase the yield and the efficiency of the manufacturing process and reduce the cost.

Abstract translation: 本发明的实施例涉及用于防止晶片断裂的曝光方法，特别是沟槽型功率MOS器件。 在一个实施例中，曝光方法包括：（a）提供衬底; （b）在衬底上形成沟槽区域和非沟槽区域; （c）在热板上承载基板，所述加热板具有对应于所述非沟槽区域的多个支撑件; 和（d）对基材进行光刻胶涂覆和烘烤程序。 本发明的曝光方法可以防止由于快速温度变化导致的晶片断裂，从而提高制造工艺的产量和效率，并降低成本。

公开(公告)号：US06727189B2

公开(公告)日：2004-04-27

申请号：US10105507

申请日：2002-03-26

Applicant: Chuan-Yi Wang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Chi-Ping Chung

Inventor： Chuan-Yi Wang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Chi-Ping Chung

IPC: H01L21302

CPC classification number: G01N1/32 ,  G01N1/4044 ,  G01N2033/0095

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract translation: 本发明的实施例涉及将砷注入晶片​​以快速检测在晶片上是否存在诸如铁，铝或锰的金属污染物。 根据本发明的一个方面，一种用于检测硅芯片的金属污染的方法包括将砷离子注入到硅芯片中，并用化学蚀刻溶液蚀刻硅芯片。 通过观察由砷离子和金属污染物之间的反应引起的硅芯片上的硅坑的发生以及用化学蚀刻溶液的蚀刻来检测是否存在任何金属污染。

公开(公告)号：US5824234A

公开(公告)日：1998-10-20

申请号：US725122

申请日：1996-10-02

Applicant: Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

Inventor： Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/00

CPC classification number: H01L21/31138 ,  H01L24/03 ,  H01L2224/0381 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029

Abstract: The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer with a fluorine-containing gas by which a fluorine-containing layer is formed on a surface of said bonding pad structure; and b) removing the fluorine-containing layer for reducing a contact resistance of said bonding pad structure.

Abstract translation: 本发明提供一种形成接触电阻低的焊盘的方法。 该方法包括以下步骤：a）在具有金属层的衬底上形成焊盘结构，在所述金属层上形成钝化层，并用形成含氟层的含氟气体蚀刻钝化层 所述焊盘结构的表面; 以及b）除去所述含氟层以降低所述接合焊盘结构的接触电阻。

公开(公告)号：US06380072B2

公开(公告)日：2002-04-30

申请号：US09725602

申请日：2000-11-29

Applicant: John Chu ,  Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

Inventor： John Chu ,  Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

IPC: H01L214763

CPC classification number: H01L21/02

Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a). providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectric layer on the conductive layer, d) forming a titanium nitride layer directly on the dielectric layer without contacting the conductive layer, and e) patternizing the titanium nitride layer, the dielectric layer and the conductive layer, wherein the dielectric layer is used for avoiding spontaneous electrochemical reaction between the titanium nitride layer and the conductive layer,

Abstract translation: 提供了一种制造具有优异金属化的半导体器件的方法。 该方法包括以下步骤：a）。 提供半导体衬底，b）在所述半导体衬底上形成导电层，c）在所述导电层上形成电介质层，d）直接在所述电介质层上形成氮化钛层而不与所述导电层接触，e）使 氮化钛层，电介质层和导电层，其中介电层用于避免氮化钛层和导电层之间的自发电化学反应，

公开(公告)号：US6010938A

公开(公告)日：2000-01-04

申请号：US192018

申请日：1998-11-11

Applicant: Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

Inventor： Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

IPC: H01L21/00

CPC classification number: H01L28/20 ,  H01L27/1112

Abstract: The present invention provides a new method for making a load resistor in a semiconductor chip. According to the new method, a linear-shaped doped polysilicon layer is formed onto the surface of the semiconductor chip that comprises a Si substrate and an NSG layer. This layer functions as a conductive path. A slot is formed in this layer by removing a section from the conductive path. This slot reaches down to the NSG layer effectively cutting off the polysilicon layer. Then, a rugged polysilicon layer is evenly deposited onto the surface of the slot for connection of the conductive path. The polysilicon layer over the slot and the doped polysilicon layer defines the load resistor. The result is a high resistance value with usage of only a small space.

Abstract translation: 本发明提供一种在半导体芯片中制造负载电阻的新方法。 根据新方法，在包括Si衬底和NSG层的半导体芯片的表面上形成线状掺杂多晶硅层。 该层用作导电路径。 通过从导电路径去除一部分，在该层中形成槽。 该槽向下到达NSG层，有效地切断了多晶硅层。 然后，将坚固的多晶硅层均匀地沉积到槽的表面上以连接导电路径。 槽上的多晶硅层和掺杂多晶硅层限定了负载电阻。 结果是具有仅较小空间的高电阻值。