公开(公告)号：US06303436B1

公开(公告)日：2001-10-16

申请号：US09400178

申请日：1999-09-21

Applicant: Kuan-Chou Sung

Inventor： Kuan-Chou Sung

IPC: H01L21336

CPC classification number: H01L27/11273 ,  H01L27/112 ,  Y10S438/923

Abstract: A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the nitride layer and the substrate to form plural trenches; a gate oxide layer being formed on surfaces of each trench; then, implanting n+-type ions into the substrate beneath the pad oxide layer and between each two adjacent trenches; and, forming a polysilicon layer on the gate oxide and pad oxide; finally, implanting n+-type ions into the substrate beneath the gate oxide layer on bottoms of selected trenches. And, it is appreciated that the sequence of the formation of plural trenches and implanting n+-type ions into substrate between each trench can be reversed in the embodiment without affecting subsequent steps.

Abstract translation: 制造一种沟槽掩模ROM单元的方法包括以下步骤：提供轻掺杂p衬底的衬底，在衬底上依次形成衬垫氧化物层和氮化物层; 蚀刻衬垫氧化物层，氮化物层和衬底以形成多个沟槽; 在每个沟槽的表面上形成栅氧化层; 然后，将n +型离子注入衬底氧化物层下面和每两个相邻沟槽之间的衬底中; 并且在栅极氧化物和衬垫氧化物上形成多晶硅层; 最后，将n +型离子注入到选定沟槽底部的栅氧化层下方的衬底中。 并且，应当理解，在该实施例中，多个沟槽的形成顺序和每个沟槽之间的n +型离子注入到衬底中可以颠倒，而不影响随后的步骤。

公开(公告)号：US06235592B1

公开(公告)日：2001-05-22

申请号：US09400177

申请日：1999-09-21

Applicant: Kuan-Chou Sung

Inventor： Kuan-Chou Sung

IPC: H01L218236

CPC classification number: H01L27/11273

Abstract: A method for forming a Trench Mask ROM cell comprises the steps of: Providing a substrate doped lightly with p-type dopant; forming plural trenches and then, forming a gate layer on each trench, further, implanting n+-type ions on substrate beneath the gate oxide layer on bottom of each trench and position between each two adjacent trench; and then, forming a nitride layer on the gate oxide layer; forming an oxide layer on the nitride layer and each trench being filled with the oxide layer; and removing the oxide layer and the nitride layer of partial trenches, namely, partial trenches reserving the oxide and the nitride layer to define coding regions of the Trench Mask ROM cell; finally, depositing a polysilicon layer on the top surfaces of the substrate wherein the polysilicon being word line of the Trench Mask ROM cell.

Abstract translation: 形成沟槽掩模ROM单元的方法包括以下步骤：提供用p型掺杂剂轻掺杂的衬底; 形成多个沟槽，然后在每个沟槽上形成栅极层，此外，在每个沟槽的底部的栅极氧化物层下方的衬底下注入n +型离子，并且在每个两个相邻沟槽之间的位置; 然后在栅氧化层上形成氮化物层; 在所述氮化物层上形成氧化物层，并且每个沟槽被所述氧化物层填充; 去除部分沟槽的氧化物层和氮化物层，即保留氧化物和氮化物层的部分沟槽，以限定沟槽掩模ROM单元的编码区域; 最后，在衬底的顶表面上沉积多晶硅层，其中多晶硅是沟槽掩模ROM单元的字线。

公开(公告)号：US6010938A

公开(公告)日：2000-01-04

申请号：US192018

申请日：1998-11-11

Applicant: Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

Inventor： Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

IPC: H01L21/00

CPC classification number: H01L28/20 ,  H01L27/1112

Abstract: The present invention provides a new method for making a load resistor in a semiconductor chip. According to the new method, a linear-shaped doped polysilicon layer is formed onto the surface of the semiconductor chip that comprises a Si substrate and an NSG layer. This layer functions as a conductive path. A slot is formed in this layer by removing a section from the conductive path. This slot reaches down to the NSG layer effectively cutting off the polysilicon layer. Then, a rugged polysilicon layer is evenly deposited onto the surface of the slot for connection of the conductive path. The polysilicon layer over the slot and the doped polysilicon layer defines the load resistor. The result is a high resistance value with usage of only a small space.

Abstract translation: 本发明提供一种在半导体芯片中制造负载电阻的新方法。 根据新方法，在包括Si衬底和NSG层的半导体芯片的表面上形成线状掺杂多晶硅层。 该层用作导电路径。 通过从导电路径去除一部分，在该层中形成槽。 该槽向下到达NSG层，有效地切断了多晶硅层。 然后，将坚固的多晶硅层均匀地沉积到槽的表面上以连接导电路径。 槽上的多晶硅层和掺杂多晶硅层限定了负载电阻。 结果是具有仅较小空间的高电阻值。

公开(公告)号：US6124178A

公开(公告)日：2000-09-26

申请号：US383374

申请日：1999-08-26

Applicant: Kuan-Chou Sung ,  Chien Chou ,  Steve Hsu ,  Elmer Chen

Inventor： Kuan-Chou Sung ,  Chien Chou ,  Steve Hsu ,  Elmer Chen

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/02129 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  Y10S438/952

Abstract: A method for forming a MOSFET device on a semiconductor substrate is disclosed here. First, a gate oxide layer, a polysilicon layer, a metal silicide layer and a silicon oxynitride layer are formed on the semiconductor substrate in sequence. Then, the silicon oxynitride layer, the metal silicide layer, the polysilicon layer and the gate oxide layer are etched to define a gate pattern. The sidewall spacers are formed on the sidewalls of the gate structure. The source and drain areas are defined by forming the doping areas in the semiconductor substrate. Next, a non-doped dielectric layer is formed above the semiconductor substrate to cover the gate structure, the sidewall spacers and the source/drain areas. An annealing procedure is next performed about 10 to 15 minutes at a temperature of about 800 to 850.degree. C. Then, a dielectric layer is formed on said non-doped dielectric layer.

Abstract translation: 这里公开了在半导体衬底上形成MOSFET器件的方法。 首先，依次在半导体衬底上形成栅氧化层，多晶硅层，金属硅化物层和氧氮化硅层。 然后，蚀刻硅氮氧化物层，金属硅化物层，多晶硅层和栅极氧化物层以限定栅极图案。 侧壁间隔件形成在栅极结构的侧壁上。 源极和漏极区域通过在半导体衬底中形成掺杂区域来限定。 接下来，在半导体衬底的上方形成非掺杂电介质层以覆盖栅极结构，侧壁间隔物和源极/漏极区域。 接下来在约800至850℃的温度下进行约10至15分钟的退火程序。然后，在所述非掺杂电介质层上形成电介质层。