公开(公告)号：US06812148B2

公开(公告)日：2004-11-02

申请号：US10219094

申请日：2002-08-13

Applicant: Chieh-Ju Chang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Yifu Chung

Inventor： Chieh-Ju Chang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Yifu Chung

IPC: H01L21311

CPC classification number: H01L21/28238 ,  C23C8/02 ,  C23C8/10 ,  C23C8/80 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/7621 ,  H01L29/518

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.

Abstract translation: 本发明的实施例涉及一种用于在凹槽LOCOS工艺中防止栅极氧化物稀化的方法。 多个沟槽由图案化的衬垫氧化物和图案化的氮化硅层分离。去除图案化的氮化硅层和图案化衬垫氧化物层，以暴露衬底的表面作为半导体器件的有效区域。 在衬底上的有源区域中的离子驱动通过在预定温度和足够量的氧气下引导氧和氮流向衬底来进行，以至少基本上防止在场氧化物区域上形成氮化硅 。 该方法还包括在有源区上形成牺牲氧化物层，去除牺牲氧化物层以暴露有源区，以及在有源区上形成栅极氧化物层。

公开(公告)号：US06727189B2

公开(公告)日：2004-04-27

申请号：US10105507

申请日：2002-03-26

Applicant: Chuan-Yi Wang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Chi-Ping Chung

Inventor： Chuan-Yi Wang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Chi-Ping Chung

IPC: H01L21302

CPC classification number: G01N1/32 ,  G01N1/4044 ,  G01N2033/0095

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract translation: 本发明的实施例涉及将砷注入晶片​​以快速检测在晶片上是否存在诸如铁，铝或锰的金属污染物。 根据本发明的一个方面，一种用于检测硅芯片的金属污染的方法包括将砷离子注入到硅芯片中，并用化学蚀刻溶液蚀刻硅芯片。 通过观察由砷离子和金属污染物之间的反应引起的硅芯片上的硅坑的发生以及用化学蚀刻溶液的蚀刻来检测是否存在任何金属污染。

公开(公告)号：US06245608B1

公开(公告)日：2001-06-12

申请号：US09332125

申请日：1999-06-14

Applicant: Tsai-Sen Lin ,  Chon-Shin Jou ,  Der-Tsyr Fan

Inventor： Tsai-Sen Lin ,  Chon-Shin Jou ,  Der-Tsyr Fan

IPC: H01L218238

CPC classification number: H01L21/28512 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823871 ,  Y10S438/919

Abstract: A method of contact ion implantation is disclosed. Only one mask and a dosage-enhanced implantation is utilized to form different types of doped contact regions. A blanket ion implantation is first carried out, and all the contact regions of first and second type are formed with the first conductive type impurities. Then a mask is defined to cover the first type contact regions and expose the second type regions. A second ion implantation is now carried out to implant impurity ions of second conductive type into the second type contact regions. The dosage of these second conductive type ions is determined so that, the second type contact regions are convert from the first conductive type into section conductive type.

Abstract translation: 公开了接触离子注入的方法。 仅使用一个掩模和剂量增强的注入来形成不同类型的掺杂接触区域。 首先进行覆盖式离子注入，并且第一和第二类型的所有接触区域由第一导电类型的杂质形成。 然后，限定掩模以覆盖第一类型接触区域并暴露第二类型区域。 现在执行第二离子注入以将第二导电类型的杂质离子注入到第二类型接触区域中。 确定这些第二导电型离子的剂量使得第二类型的接触区域从第一导电类型转换为导电型。

公开(公告)号：US06492188B1

公开(公告)日：2002-12-10

申请号：US09265962

申请日：1999-03-11

Applicant: Tsai-Sen Lin ,  Bor-Shiun Wu ,  Chou-Shin Jou ,  Tings Wang

Inventor： Tsai-Sen Lin ,  Bor-Shiun Wu ,  Chou-Shin Jou ,  Tings Wang

IPC: G01R3126

CPC classification number: H01L22/24

Abstract: The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.

Abstract translation: 金属防反射涂层（ARC）层的质量监测方法技术领域本发明涉及金属防反射涂层（ARC）层的质量监测方法，更具体地说，涉及金属ARC层质量的快速准确的监测方法。 通过根据本发明，将包含ARC层的硅晶片浸入酸性（例如显影剂）或碱性溶液中约200-300秒，在金属ARC层的弱点处发生空隙（缺陷 ）由于这些化学溶液增强的电化学电池效应，然后可以通过诸如KLA仪器的晶片缺陷检查器计数多少个缺陷，以便可以通过该缺陷数来监测金属ARC层的质量。 此外，由于用作晶片缺陷检查器的样品的硅晶片简单地来自生产线，即显影过程，而不是来自其他附加处理，所述方法允许快速且准确地监测金属ARC层的质量。

公开(公告)号：US06677216B2

公开(公告)日：2004-01-13

申请号：US10263397

申请日：2002-10-01

Applicant: Chun-Pey Cho ,  Tsai-Sen Lin ,  Chou-Shin Jou ,  Chuan-Yi Wang ,  Jen-Chieh Chang ,  Yi-Fu Chung ,  Huei-Ping Hsieh

Inventor： Chun-Pey Cho ,  Tsai-Sen Lin ,  Chou-Shin Jou ,  Chuan-Yi Wang ,  Jen-Chieh Chang ,  Yi-Fu Chung ,  Huei-Ping Hsieh

IPC: H01L2120

CPC classification number: H01L28/60 ,  H01L21/28518 ,  Y10S438/952

Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.

Abstract translation: 本发明的实施例涉及一种制造IC电容器的方法。 在一个实施例中，该方法包括提供衬底，在衬底上形成多晶硅化物层，并在多晶硅化物层上形成绝缘非晶硅层。 绝缘非晶硅层用作防反射层。 该方法还包括将n型离子注入到绝缘非晶硅层中以将绝缘非晶硅层转变为导电非晶硅层，以及图案化多晶硅化物层和导电非晶硅层，以在衬底上形成底部电极。 在底部电极和基板上形成电介质层，在电介质层上形成导体层。 将导体层图案化以在电介质层上形成顶部电极。