公开(公告)号：US06727189B2

公开(公告)日：2004-04-27

申请号：US10105507

申请日：2002-03-26

Applicant: Chuan-Yi Wang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Chi-Ping Chung

Inventor： Chuan-Yi Wang ,  Tsai-Sen Lin ,  Chon-Shin Jou ,  Chi-Ping Chung

IPC: H01L21302

CPC classification number: G01N1/32 ,  G01N1/4044 ,  G01N2033/0095

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract translation: 本发明的实施例涉及将砷注入晶片​​以快速检测在晶片上是否存在诸如铁，铝或锰的金属污染物。 根据本发明的一个方面，一种用于检测硅芯片的金属污染的方法包括将砷离子注入到硅芯片中，并用化学蚀刻溶液蚀刻硅芯片。 通过观察由砷离子和金属污染物之间的反应引起的硅芯片上的硅坑的发生以及用化学蚀刻溶液的蚀刻来检测是否存在任何金属污染。

公开(公告)号：US6153849A

公开(公告)日：2000-11-28

申请号：US240415

申请日：1999-01-29

Applicant: Ken-Yuan Yung ,  Ming-Shue Yan ,  Tsar-Yi Chen ,  Wen-Bing Lin ,  Chuan-Yi Wang

Inventor： Ken-Yuan Yung ,  Ming-Shue Yan ,  Tsar-Yi Chen ,  Wen-Bing Lin ,  Chuan-Yi Wang

IPC: H01J37/32 ,  H01L21/3213 ,  B23K10/00

CPC classification number: H01J37/32522 ,  H01J37/321 ,  H01L21/32137

Abstract: An apparatus and a method for preventing etch rate drop after a machine idle time in a plasma etch chamber are disclosed. In the apparatus, an enclosure for enclosing a top plate in the plasma etch chamber is provided which is equipped with a heater in fluid communication with the enclosure. The top plate which includes a dielectric window and an inductive coil can be heated to a temperature between about 35.degree. C. and about 45.degree. C. during machine idle time to prevent etch rate drop after the chamber is restarted. The plasma etch chamber may be an inductively coupled RF plasma etcher. The heater may be constructed by a heater housing which is in fluid communication with the enclosure, at least one heating lamp in the housing, and a blower for delivering heated air into the enclosure cavity. By utilizing the present invention novel apparatus and method, etch rate can be substantially maintained even after a machine idle time and an under-etch condition can be prevented to substantially eliminate scrap of defective wafers.

Abstract translation: 公开了一种用于在等离子体蚀刻室中的机器空闲时间之后防止蚀刻速率下降的装置和方法。 在该设备中，提供了用于封装等离子体蚀刻室中的顶板的外壳，其配备有与外壳流体连通的加热器。 在机器空闲时间期间，包括电介质窗和感应线圈的顶板可以加热到约35℃至约45℃之间的温度，以防止室重新启动后的蚀刻速率下降。 等离子体蚀刻室可以是感应耦合RF等离子体蚀刻器。 加热器可以由与壳体流体连通的加热器壳体，壳体中的至少一个加热灯和用于将加热的空气输送到外壳腔中的鼓风机构成。 通过利用本发明的新颖的装置和方法，即使在机器空闲时间之后也可以基本上保持蚀刻速率，并且可以防止蚀刻不足的情况基本上消除有缺陷晶片的碎屑。

公开(公告)号：US6134850A

公开(公告)日：2000-10-24

申请号：US243571

申请日：1999-02-03

Applicant: Ming-Chu Hui ,  Bo-Han Hsieh ,  Chuan-Yi Wang ,  Yien-Yuan Yang

Inventor： Ming-Chu Hui ,  Bo-Han Hsieh ,  Chuan-Yi Wang ,  Yien-Yuan Yang

IPC: E04B5/43 ,  E04H9/02

CPC classification number: E04H9/021 ,  E04B5/43

Abstract: A method for earthquake-proof mounting a semiconductor process machine on a removable floor (or a raised floor) in a semiconductor fabrication plant. In the method, a modified I-beam which has a horizontally extending upper flange is provided for mounting under a removable floor and attaching through the floor directly to a process machine situated on top of the floor. The process machine may be attached to the modified I-beam through an L-shaped bracket that is attached to the support frame of the process machine with the horizontal flange of the bracket attached to the modified I-beam through apertures in the removable floor. The present invention further comprises an earthquake-proof mounting fixture for mounting a process machine on a removable floor in a semiconductor fabrication plant. The mounting fixture consists of essentially a modified I-beam for supporting the removable floor on a non-removable floor, the I-beam is equipped with a horizontally extending upper flange for attaching to the process machine directly through the removable floor. The present invention novel method and apparatus allows a process machine to be mounted on a removable floor in a fabrication plant to meet seismic prevention regulations imposed by government agencies for environmental protection and occupational safety. The present invention novel apparatus is especially suitable for use in mounting process machines that holds hazardous, corrosive chemicals for preventing chemicals from spilling during an earthquake, especially when the process machine is mounted on a higher floor in the plant.

Abstract translation: 一种用于在半导体制造工厂中的可移动地板（或高架地板）上安装半导体处理机的防震方法。 在该方法中，提供具有水平延伸的上凸缘的改进的工字梁，用于安装在可拆卸的地板下方并且通过地板直接附接到位于地板顶部的处理机器。 加工机器可以通过L形支架附接到经修改的工字梁上，该L形支架附接到加工机器的支撑架上，其中支架的水平​​凸缘通过可移动地板中的孔与修改的I型梁相连。 本发明还包括用于将加工机器安装在半导体制造工厂中的可移动地板上的防震安装夹具。 安装夹具基本上由改进的工字梁组成，用于支撑不可拆卸地板上的可移动地板，工字梁配备有水平延伸的上凸缘，用于通过可移动的地板直接连接到加工机。 本发明的新颖方法和装置允许将加工机器安装在制造工厂的可移动地板上，以满足政府机构对环境保护和职业安全施加的防止地震规定。 本发明的新型装置特别适用于安装防止化学物质在地震期间溢出的危险的腐蚀性化学物质的加工机械，特别是当工艺机器安装在工厂的较高楼层时。

公开(公告)号：US06677216B2

公开(公告)日：2004-01-13

申请号：US10263397

申请日：2002-10-01

Applicant: Chun-Pey Cho ,  Tsai-Sen Lin ,  Chou-Shin Jou ,  Chuan-Yi Wang ,  Jen-Chieh Chang ,  Yi-Fu Chung ,  Huei-Ping Hsieh

Inventor： Chun-Pey Cho ,  Tsai-Sen Lin ,  Chou-Shin Jou ,  Chuan-Yi Wang ,  Jen-Chieh Chang ,  Yi-Fu Chung ,  Huei-Ping Hsieh

IPC: H01L2120

CPC classification number: H01L28/60 ,  H01L21/28518 ,  Y10S438/952

Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.

Abstract translation: 本发明的实施例涉及一种制造IC电容器的方法。 在一个实施例中，该方法包括提供衬底，在衬底上形成多晶硅化物层，并在多晶硅化物层上形成绝缘非晶硅层。 绝缘非晶硅层用作防反射层。 该方法还包括将n型离子注入到绝缘非晶硅层中以将绝缘非晶硅层转变为导电非晶硅层，以及图案化多晶硅化物层和导电非晶硅层，以在衬底上形成底部电极。 在底部电极和基板上形成电介质层，在电介质层上形成导体层。 将导体层图案化以在电介质层上形成顶部电极。