公开(公告)号：US20060046207A1

公开(公告)日：2006-03-02

申请号：US11112454

申请日：2005-04-21

Applicant: Hsing Tsun Liu ,  Hsieh Hsin Huang ,  Chon-Shin Jou

Inventor： Hsing Tsun Liu ,  Hsieh Hsin Huang ,  Chon-Shin Jou

IPC: G03F7/38 ,  G03F7/40

CPC classification number: H01L21/6875

Abstract: Embodiments of the invention are directed to an exposure method for preventing wafer breakage, particularly of a trench-type power MOS device. In one embodiment, the exposure method includes: (a) providing a substrate; (b) forming a trench area and a non-trench area on the substrate; (c) carrying the substrate on a hot plate, the hot plate having a plurality of supporters corresponding to the non-trench area; and (d) performing photoresist coating and baking procedures to the substrate. The exposure method of the present invention can prevent wafer breakage due to rapid temperature variation so as to increase the yield and the efficiency of the manufacturing process and reduce the cost.

Abstract translation: 本发明的实施例涉及用于防止晶片断裂的曝光方法，特别是沟槽型功率MOS器件。 在一个实施例中，曝光方法包括：（a）提供衬底; （b）在衬底上形成沟槽区域和非沟槽区域; （c）在热板上承载基板，所述加热板具有对应于所述非沟槽区域的多个支撑件; 和（d）对基材进行光刻胶涂覆和烘烤程序。 本发明的曝光方法可以防止由于快速温度变化导致的晶片断裂，从而提高制造工艺的产量和效率，并降低成本。