公开(公告)号：US06380072B2

公开(公告)日：2002-04-30

申请号：US09725602

申请日：2000-11-29

Applicant: John Chu ,  Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

Inventor： John Chu ,  Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

IPC: H01L214763

CPC classification number: H01L21/02

Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a). providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectric layer on the conductive layer, d) forming a titanium nitride layer directly on the dielectric layer without contacting the conductive layer, and e) patternizing the titanium nitride layer, the dielectric layer and the conductive layer, wherein the dielectric layer is used for avoiding spontaneous electrochemical reaction between the titanium nitride layer and the conductive layer,

Abstract translation: 提供了一种制造具有优异金属化的半导体器件的方法。 该方法包括以下步骤：a）。 提供半导体衬底，b）在所述半导体衬底上形成导电层，c）在所述导电层上形成电介质层，d）直接在所述电介质层上形成氮化钛层而不与所述导电层接触，e）使 氮化钛层，电介质层和导电层，其中介电层用于避免氮化钛层和导电层之间的自发电化学反应，

公开(公告)号：US5037766A

公开(公告)日：1991-08-06

申请号：US466583

申请日：1990-01-17

Applicant: Ting S. Wang

Inventor： Ting S. Wang

IPC: H01L21/02 ,  H01L21/3215 ,  H01L21/336 ,  H01L27/11 ,  H01L29/786

CPC classification number: H01L28/20 ,  H01L21/32155 ,  H01L29/66757 ,  H01L29/78618 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S438/922 ,  Y10S438/98

Abstract: A method of fabricating a double layered polisilicon film with oxygen diffusion for scaled down polysilicon thin film transistor/resistor. The double layered polysilicon film structure includes: a first heavily doped polysilicon layer, produced by Low Pressure Chemical Vapor Deposition (LPCVD) system at about 610 degrees Centigrade, is used as electrodes of resistor or source/drain electrodes of a transistor, and a second layer of polysilicon, deposited by LPCVD at the temperature about 560 degrees Centigrade, is used as a resistor layer or a channel layer of a transistor.Oxygen treatment is applied at low temperature after the first polysilicon layer is defined. The oxygen present at polysilicon grain boundary blocks the dopant diffusing from the first electrode polysilicon to the second polysilicon which is used as resistor region or a channel region of a transistor. Thus, the resistor can maintain high resistivity and the transistor can maintain low threshold voltage even when they are scaled down.

Abstract translation: 一种制造具有氧扩散的双层硅胶膜的方法，用于按比例缩小的多晶硅薄膜晶体管/电阻器。 双层多晶硅膜结构包括：用于在610摄氏度的低压化学气相沉积（LPCVD）系统产生的第一重掺杂多晶硅层，用作晶体管的电阻或源极/漏极的电极，第二 通过LPCVD在约560摄氏度的温度下沉积的多晶硅层被用作晶体管的电阻层或沟道层。 在定义第一多晶硅层之后，在低温下进行氧化处理。 存在于多晶硅晶界处的氧阻挡从第一电极多晶硅向第二多晶硅扩散的掺杂​​剂，该第二多晶硅用作电阻区或晶体管的沟道区。 因此，电阻器可以保持高电阻率，并且晶体管即使在按比例缩小时也可以保持低阈值电压。

公开(公告)号：US06544847B2

公开(公告)日：2003-04-08

申请号：US09915928

申请日：2001-07-26

Applicant: Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

Inventor： Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

IPC: H01L2968

CPC classification number: H01L27/11521 ,  G11C2216/10 ,  H01L27/11558

Abstract: The present invention discloses a method for fabricating a non-volatile memory structure from a single layer of polysilicon in a semiconductor substrate, wherein the semiconductor substrate with two active areas, first and second, are divided by isolation regions. In accordance with this method, a doped buried layer is formed in the first active area. Then, a first floating gate is formed on the buried layer and a second floating gate is formed on the second active area from the single layer of polysilicon. Next, two doped regions are formed at opposite sides of the second floating gate in the second active areas. Finally, a floating gate connection line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential.

Abstract translation: 本发明公开了一种从半导体衬底中的单层多晶硅制造非易失性存储器结构的方法，其中具有第一和第二有效区域的半导体衬底被隔离区划分。 根据该方法，在第一有源区域中形成掺杂掩埋层。 然后，在掩埋层上形成第一浮栅，并且在第二有源区上形成第二浮栅，该第二浮栅是单层多晶硅。 接下来，在第二有源区域中的第二浮栅的相对侧形成两个掺杂区。 最后，采用浮栅连接线来连接第一和第二浮栅，以确保两个浮栅处于相同的电位。

公开(公告)号：US5747378A

公开(公告)日：1998-05-05

申请号：US863402

申请日：1997-05-27

Applicant: Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting-S. Wang

Inventor： Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting-S. Wang

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/22

CPC classification number: H01L27/10873 ,  H01L21/2255 ,  H01L21/823418 ,  H01L29/6656 ,  H01L29/66575 ,  Y10S148/144

Abstract: A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.

Abstract translation: 本文公开了一种用于形成动态随机存取存储器单元的无损耗掺杂的方法。 磷酸硅玻璃作为扩散源沉积。 在热退火过程中，磷酸硅玻璃的磷离子可以扩散到衬底中，以通过高温形成源/漏区。 接下来，通过热氧化工艺在栅电极和衬底的表面上形成热氧化层。 在随后的热处理过程中，热氧化物层可以防止离子扩散到衬底中。 因此，本发明可以减少动态随机存取存储器的损坏。

公开(公告)号：US06324097B1

公开(公告)日：2001-11-27

申请号：US09383373

申请日：1999-08-26

Applicant: Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

Inventor： Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

IPC: G11C1604

CPC classification number: H01L27/11521 ,  G11C2216/10 ,  H01L27/11558

Abstract: The present invention discloses a single poly non-volatile memory structure including a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate. While one of the doped regions is biased to a voltage level, electrons would eject from the other doped region and trapped in the floating gates, thereby preserving information in this memory structure.

Abstract translation: 本发明公开了一种单一的多元非易失性存储结构，其包括半导体衬底，两个有源区被隔离区划分。 掺杂有N型杂质的控制栅极嵌入在第一有源区中，并且在其上形成第一浮栅。 在第二有源区的衬底上形成第二浮栅，并且在衬底中的第二有源区的相对侧注入两个掺杂区。 采用浮动栅极线连接第一和第二浮栅，以确保两个浮动栅极处于相同的电位。 当控制栅极偏置到电压电平时，电压电平将耦合到第一浮置栅极，以便使第二浮置栅极与第一浮置栅极保持相同的电位。 虽然一个掺杂区域被偏置到电压电平，但电子将从另一个掺杂区域弹出并被捕获在浮动栅极中，从而保留该存储器结构中的信息。

公开(公告)号：US5882984A

公开(公告)日：1999-03-16

申请号：US728305

申请日：1996-10-09

Applicant: Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

Inventor： Der-Tsyr Fan ,  Chon-Shin Jou ,  Ting S. Wang

IPC: H01L21/762 ,  H01L21/8242 ,  H01L21/76

CPC classification number: H01L27/10844 ,  H01L21/76202

Abstract: The present invention is a method for increasing the refresh time of DRAM. This invention is for decreasing the stress between the bird's beak of field oxide and silicon substrate by using fluorine ion implant before field oxidation and the optimal structure of LOCOS to effectively preventing the current leakage from the bird's beak of field oxide. Therefore, this invention can increase the refresh time of DRAM and greatly enhance the performance in DRAM.

Abstract translation: 本发明是增加DRAM刷新时间的方法。 本发明是通过在场氧化之前使用氟离子注入和LOCOS的最佳结构来减少场氧化物的鸟嘴和硅衬底之间的应力，以有效地防止来自场氧化物的鸟喙的电流泄漏。 因此，本发明可以增加DRAM的刷新时间并大大提高DRAM的性能。