公开(公告)号：US08173487B2

公开(公告)日：2012-05-08

申请号：US12530552

申请日：2008-04-01

Applicant: Masao Urayama ,  Masashi Kawasaki ,  Hideo Ohno

Inventor： Masao Urayama ,  Masashi Kawasaki ,  Hideo Ohno

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L29/7869 ,  H01L29/78696 ,  Y10S438/922

Abstract: A thin-film transistor (1) of the present invention includes an insulating substrate (2), a gate electrode (3) which has a predetermined shape and is formed on the insulating substrate (2), a gate insulating film (4) formed on the gate electrode (3), and a semiconductor layer (5) which is polycrystalline ZnO and is formed on the gate insulating film (4). The semiconductor layer (5) is immersed in a solution in which impurities are dissolved so that the impurities are selectively added to a grain boundary part of the polycrystalline ZnO film. Subsequently, a source electrode (6) and a drain electrode (7) are formed so as to have a predetermined shape. Next, a protection layer (8) is formed on the source electrode (6) and the drain electrode (7). Thus, a thin-film transistor which has a good subthreshold characteristic and has a zinc oxide film as a base of an active layer can be realized.

Abstract translation: 本发明的薄膜晶体管（1）包括绝缘基板（2），具有预定形状并形成在绝缘基板（2）上的栅电极（3），形成有栅极绝缘膜（4） 在栅电极（3）上形成半导体层（5），并形成在栅极绝缘膜（4）上。 将半导体层（5）浸渍在杂质溶解的溶液中，使杂质选择性地添加到多晶ZnO膜的晶界部分。 随后，源电极（6）和漏电极（7）形成为具有预定形状。 接下来，在源电极（6）和漏电极（7）上形成保护层（8）。 因此，可以实现具有良好的亚阈值特性并且具有氧化锌膜作为有源层的基底的薄膜晶体管。

公开(公告)号：US20100117116A1

公开(公告)日：2010-05-13

申请号：US12690778

申请日：2010-01-20

Applicant: Ulrich Glaser ,  Harald Gossner ,  Kai Esmark

Inventor： Ulrich Glaser ,  Harald Gossner ,  Kai Esmark

IPC: H01L29/87

CPC classification number: H01L29/7436 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/87 ,  H01L2924/0002 ,  Y10S438/919 ,  Y10S438/922 ,  Y10S438/923 ,  H01L2924/00

Abstract: An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

公开(公告)号：US5034782A

公开(公告)日：1991-07-23

申请号：US422762

申请日：1989-10-17

Applicant: Toru Koizumi ,  Hidemasa Mizutani

Inventor： Toru Koizumi ,  Hidemasa Mizutani

IPC: H01L21/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/32 ,  H01L29/861

CPC classification number: H01L29/861 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02647 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/32 ,  Y10S438/921 ,  Y10S438/922

Abstract: A semiconductor commutator is provided with first and second semiconductor regions joined at a junction formed therebetween. The first semiconductor region is of the first conductivity type at the second semiconductor region is of the opposite conductivity type. A grain boundary is provided near the junction and within a region, through which a carrier passes, between electrodes respectively provided on the semiconductor regions.

公开(公告)号：US3128530A

公开(公告)日：1964-04-14

申请号：US2864460

申请日：1960-05-12

Applicant: ASS ELECT IND

Inventor： LINDSAY ROUSE ROBERT ,  JAMES WAKEFIELD ,  CHARLES NEWMAN RONALD

IPC: C30B15/36 ,  C30B31/02 ,  H01L21/00 ,  H01L21/18 ,  H01L21/208 ,  H01L21/22 ,  H01L21/322 ,  H01L29/06 ,  H01L29/167 ,  H01L29/36 ,  H01L29/73 ,  H01L29/86

CPC classification number: H01L29/73 ,  C30B15/36 ,  C30B31/02 ,  H01L21/00 ,  H01L21/18 ,  H01L21/22 ,  H01L21/322 ,  H01L29/06 ,  H01L29/167 ,  H01L29/36 ,  H01L29/86 ,  Y10S148/003 ,  Y10S148/033 ,  Y10S148/049 ,  Y10S148/051 ,  Y10S148/115 ,  Y10S148/122 ,  Y10S148/151 ,  Y10S438/922

公开(公告)号：US20070158750A1

公开(公告)日：2007-07-12

申请号：US11604519

申请日：2006-11-27

Applicant: Ulrich Glaser ,  Harold Gossner ,  Kai Esmark

Inventor： Ulrich Glaser ,  Harold Gossner ,  Kai Esmark

IPC: H01L29/76

CPC classification number: H01L29/7436 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/87 ,  H01L2924/0002 ,  Y10S438/919 ,  Y10S438/922 ,  Y10S438/923 ,  H01L2924/00

Abstract: An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

Abstract translation: 集成电路装置包括Shockley二极管或晶闸管。 在植入p型阱期间，二极管或晶闸管的内部区域被完全或部分屏蔽。 这导致Shockley二极管或具有改善的电性能的晶闸管，特别是关于用作ESD保护元件的晶闸管。

公开(公告)号：US06307248B1

公开(公告)日：2001-10-23

申请号：US09289890

申请日：1999-04-12

Applicant: Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

Inventor： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

IPC: H01L2900

CPC classification number: H01L27/11803 ,  Y10S438/922

Abstract: A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

Abstract translation: 描述了在限定反熔丝窗口中使用未掺杂的多晶硅膜作为掩模来制造抗熔丝电池的方法。 在半导体衬底的表面上设置一层氧化硅。 第一未掺杂的多晶硅层沉积在氧化硅层上。 第一未掺杂的多晶硅层被图案化以形成掩模的光致抗蚀剂层覆盖。 将第一未掺杂的多晶硅层和一部分氧化硅层蚀刻掉，其中它们不被掩模覆盖以形成电池开口。 除去孔中的掩模和剩余的氧化硅。 绝缘层沉积在第一未掺杂多晶硅层的表面上并且在电池开口内。 第二多晶硅层沉积在绝缘层上并掺杂。 将第二多晶硅层图案化以形成抗熔丝电池。 形成栅电极和源极和漏极区，完成集成电路器件的制造。

公开(公告)号：US5572044A

公开(公告)日：1996-11-05

申请号：US471161

申请日：1995-06-06

Applicant: Toru Koizumi ,  Hidemasa Mizutani

Inventor： Toru Koizumi ,  Hidemasa Mizutani

IPC: H01L21/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/32 ,  H01L29/861 ,  H01L31/036

CPC classification number: H01L29/861 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02647 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/32 ,  Y10S438/921 ,  Y10S438/922

Abstract: A semiconductor commutator which is constructed by joining a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type, wherein there is provided a grain boundary which is located near a junction surface of the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type so as not to cross said junction surface.

Abstract translation: 一种半导体换向器，其通过连接第一导电类型的半导体区域和第二导电类型的半导体区域而构成，其中提供了位于第一导电类型的半导体区域的接合表面附近的晶界和 所述第二导电类型的半导体区域不会穿过所述接合面。

公开(公告)号：US5529954A

公开(公告)日：1996-06-25

申请号：US480733

申请日：1995-06-07

Applicant: Tadashi Iijima ,  Hisako Ono ,  Yukihiro Ushiku ,  Akira Nishiyama ,  Naomi Nakasa

Inventor： Tadashi Iijima ,  Hisako Ono ,  Yukihiro Ushiku ,  Akira Nishiyama ,  Naomi Nakasa

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/28

CPC classification number: H01L21/76834 ,  H01L21/28512 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76874 ,  H01L21/76882 ,  H01L21/76886 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/035 ,  Y10S438/922

Abstract: A semiconductor device includes a first metal film formed on a semiconductor substrate, a second metal film formed on the first metal film and containing silver as a main component, and a protective film containing a metal element of the first metal film and covering at least the upper surface of the second metal film. The protective film is formed by annealing in an atmosphere containing a predetermined element. That is, the metal element of the first metal film is diffused into the second metal film and reacts with the predetermined element in the atmosphere on the surface of the second metal film, thereby forming the protective film. Aggregation of silver is prevented in the presence of the protective film.

Abstract translation: 半导体器件包括形成在半导体衬底上的第一金属膜，形成在第一金属膜上并含有银作为主要成分的第二金属膜和包含第一金属膜的金属元素的保护膜，并且至少覆盖 第二金属膜的上表面。 保护膜通过在含有规定元素的气氛中进行退火而形成。 也就是说，第一金属膜的金属元素扩散到第二金属膜中并与第二金属膜的表面上的大气中的预定元素反应，从而形成保护膜。 在保护膜的存在下防止银的聚集。

公开(公告)号：US4155785A

公开(公告)日：1979-05-22

申请号：US856941

申请日：1977-12-02

Applicant: Jerome J. Cuomo ,  Thomas H. DiStefano ,  Robert Rosenberg

Inventor： Jerome J. Cuomo ,  Thomas H. DiStefano ,  Robert Rosenberg

IPC: H01L31/04 ,  H01L31/0368 ,  H01L31/068 ,  H01L31/07 ,  H01L21/22

CPC classification number: H01L31/0368 ,  H01L31/03682 ,  H01L31/068 ,  H01L31/07 ,  Y02E10/546 ,  Y02E10/547 ,  Y10S148/128 ,  Y10S438/922

Abstract: The practice of this disclosure obtains a relatively high efficiency operation for a crystalline semiconductor solar cell containing various defects of the linear and planar types. Linear defects include screw dislocations as well as full and partial dislocations. Planar defects include twins, stacking faults, grain boundaries and surfaces. Such defects normally contain recombination centers at which electrons and holes generated in the semiconductor region recombine with loss to the external current of the charge carried thereby. Through application of the principles of this invention, especial dopant concentrations and conductivity regions are established in a finite region around the linear and planar defects so that electrons and holes which are generated in the semiconductor region by incident radiation are substantially collected for external current as consequence thereof.

Abstract translation: 本公开的实践获得了包含线性和平面类型的各种缺陷的晶体半导体太阳能电池的相对高效率的操作。 线性缺陷包括螺旋位错以及全部和部分位错。 平面缺陷包括双胞胎，堆垛层错，晶界和表面。 这样的缺陷通常包含复合中心，在半导体区域中产生的电子和空穴与由此携带的电荷的外部电流的损耗重新组合。 通过应用本发明的原理，在围绕线性和平面缺陷的有限区域内建立了特殊的掺杂剂浓度和导电性区域，使得通过入射辐射在半导体区域中产生的电子和空穴基本上被收集用于外部电流 其中。

公开(公告)号：US4082889A

公开(公告)日：1978-04-04

申请号：US652962

申请日：1976-01-28

Applicant: Thomas Herman DiStefano

Inventor： Thomas Herman DiStefano

IPC: C09K11/08 ,  H01J9/22 ,  H01J29/20 ,  H01J31/12 ,  B32B5/16

CPC classification number: C09K11/08 ,  H01J29/20 ,  H01J31/12 ,  H01J9/221 ,  Y10S148/12 ,  Y10S148/122 ,  Y10S148/15 ,  Y10S148/157 ,  Y10S438/922 ,  Y10T428/256 ,  Y10T428/2991

Abstract: This disclosure provides a polycrystalline semiconductor material which has a high luminous efficiency because of an especial profile of impurity concentration within each grain thereof. The regions immediately adjacent to the grain surfaces or grain boundaries are preferentially and selectively doped with impurity atoms to achieve a relatively high concentration of majority carriers of the same conductivity type as is in the grain center. As a result of the noted doping profile in the material, minority carriers which are excited within each grain by externally originated radiation are confined to the central portion of the grain where they emit electromagnetic radiation by efficient luminescent recombination. The material of this disclosure in polycrystalline thin film form obtains a high resolution screen for an electron beam optical display device.