公开(公告)号：US07531462B2

公开(公告)日：2009-05-12

申请号：US11444301

申请日：2006-06-01

申请人： Katsujiro Tanzawa ,  Norihiko Tsuchiya ,  Junji Sugamoto ,  Yukihiro Ushiku

发明人： Katsujiro Tanzawa ,  Norihiko Tsuchiya ,  Junji Sugamoto ,  Yukihiro Ushiku

IPC分类号： H01L21/302

CPC分类号： H01L22/12 ,  G01N21/9501

摘要： A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.

摘要翻译： 一种检查半导体晶片的方法，包括用化学溶液去除半导体晶片上的器件结构膜以暴露半导体晶片的晶体表面; 用保护半导体晶片的晶体表面的掩模材料涂覆作为半导体晶片的晶体表面的一部分的保护区域; 选择性地蚀刻半导体晶片，从而在未涂覆有掩模材料的半导体晶片的晶体表面的一部分的非保护区域中出现晶体缺陷，在晶体表面涂覆有掩模材料之后 ; 在选择性蚀刻之后去除掩模材料; 使用光学缺陷检查装置或光束型缺陷检查装置进行保护区域和非保护区域的定量测量; 并根据测量结果计算半导体晶片基底的晶体缺陷数。

公开(公告)号：US07529634B2

公开(公告)日：2009-05-05

申请号：US10999938

申请日：2004-12-01

申请人： Kunihiro Mitsutake ,  Yukihiro Ushiku

发明人： Kunihiro Mitsutake ,  Yukihiro Ushiku

IPC分类号： G01R31/00

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of searching for clustering faults is employed for semiconductor device manufacturing. The method enters data on faults present in a search target, calculates a frequency distribution of the faults in unit cells divided from the search target, approximates the frequency distribution by overlaying at least two discrete distribution functions, and searches for clustering faults according to weights of the discrete distribution functions on the frequency distribution.

摘要翻译： 半导体器件制造采用搜索聚类故障的方法。 该方法输入搜索目标中存在的故障的数据，计算从搜索目标划分的单位单元中的故障的频率分布，通过叠加至少两个离散分布函数近似频率分布，并根据 离散分布函数在频率分布上。

公开(公告)号：US07222026B2

公开(公告)日：2007-05-22

申请号：US10107297

申请日：2002-03-28

申请人： Hiroshi Matsushita ,  Kunihiro Mitsutake ,  Yukihiro Ushiku

发明人： Hiroshi Matsushita ,  Kunihiro Mitsutake ,  Yukihiro Ushiku

IPC分类号： G01B5/28

CPC分类号： G01N21/95607 ,  G01R31/2831

摘要： An equipment for detecting faults in semiconductor integrated circuits includes a fault input unit to input fault information for the integrated circuits formed on a semiconductor wafer, a superimposing unit to superimpose the fault information with repeating units within the surface of the semiconductor wafer, and a first characteristic factor calculation unit to calculate a first characteristic factor showing a degree to which faults are repeated every repeating unit.

摘要翻译： 用于检测半导体集成电路中的故障的设备包括：故障输入单元，用于输入形成在半导体晶片上的集成电路的故障信息;叠加单元，用于在半导体晶片的表面内叠加具有重复单元的故障信息;以及第一 特征因子计算单元，计算表示每个重复单元重复故障的程度的第一特征因子。

公开(公告)号：US20060287754A1

公开(公告)日：2006-12-21

申请号：US11471675

申请日：2006-06-21

申请人： Junji Sugamoto ,  Yukihiro Ushiku ,  Kazutaka Akiyama ,  Shoichi Harakawa

发明人： Junji Sugamoto ,  Yukihiro Ushiku ,  Kazutaka Akiyama ,  Shoichi Harakawa

IPC分类号： G06F19/00

CPC分类号： G05B19/41875 ,  G05B2219/31477 ,  G05B2219/32057 ,  G05B2219/32097 ,  G05B2219/45031 ,  Y02P90/12 ,  Y02P90/20 ,  Y02P90/22

摘要： A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.

公开(公告)号：US20050233508A1

公开(公告)日：2005-10-20

申请号：US11146002

申请日：2005-06-07

申请人： Yukihiro Ushiku

发明人： Yukihiro Ushiku

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788

CPC分类号： H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/78612 ,  H01L29/78696 ,  H01L29/7881

摘要： In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

公开(公告)号：US06930359B2

公开(公告)日：2005-08-16

申请号：US10807303

申请日：2004-03-24

申请人： Yukihiro Ushiku

发明人： Yukihiro Ushiku

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L27/01

CPC分类号： H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/78612 ,  H01L29/78696 ,  H01L29/7881

摘要： In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

摘要翻译： 在具有多个SOI-Si层的半导体元件的半导体器件中，从半导体衬底的表面的元件隔离区的高度基本相等。 或者，元件隔离区域形成在半导体衬底上相同的高度，然后形成适当地不同厚度的多个SOI-Si层。 以这种方式，可以获得具有与半导体衬底基本相同的高度的元件隔离区域和具有不同高度的SOI-Si层的期望元件区域。 单晶硅膜（SOI-Si层）的厚度可以通过包括沉积非晶硅膜和施加热处理以形成外延层的另一种方法来适当地改变，并且去除不需要的部分。

公开(公告)号：US06898551B2

公开(公告)日：2005-05-24

申请号：US10418275

申请日：2003-04-18

申请人： Shuichi Samata ,  Yukihiro Ushiku ,  Akihito Yamamoto ,  Takashi Nakao ,  Takeo Furuhata

发明人： Shuichi Samata ,  Yukihiro Ushiku ,  Akihito Yamamoto ,  Takashi Nakao ,  Takeo Furuhata

IPC分类号： F04B51/00 ,  F04B49/10 ,  G01H1/00 ,  G05B23/02 ,  G21C17/00 ,  G06F19/00

CPC分类号： G05B23/0229 ,  G01H1/003 ,  G05B23/0283

摘要： A system for predicting life of a rotary machine, includes a vibration gauge configured to measure time series data of a peak acceleration of the rotary machine; a band pass filter configured to filter an analog signal of the time series data of the peak acceleration measured by the vibration gauge in a frequency band including a first analysis frequency expressed as a product of an equation including a number of rotor blades of the rotary machine and a normal frequency unique to the rotary machine; and a data processing unit configured to predict a life span of the rotary machine by characteristics of the filtered analog data of the time series data of the peak acceleration with the first analysis frequency.

摘要翻译： 一种用于预测旋转机器寿命的系统，包括配置成测量旋转机器的峰值加速度的时间序列数据的振动计; 带通滤波器，被配置为滤波由振动计测量的峰值加速度的时间序列数据的模拟信号，所述频率带包括第一分析频率的频带，所述第一分析频率表示为包括旋转机器的多个转子叶片的等式的乘积 和旋转机器唯一的正常频率; 以及数据处理单元，其被配置为通过具有第一分析频率的峰值加速度的时间序列数据的经滤波的模拟数据的特性来预测旋转机器的寿命。

公开(公告)号：US06184083B2

公开(公告)日：2001-02-06

申请号：US09105958

申请日：1998-06-29

申请人： Yoshitaka Tsunashima ,  Kiyotaka Miyano ,  Yukihiro Ushiku

发明人： Yoshitaka Tsunashima ,  Kiyotaka Miyano ,  Yukihiro Ushiku

IPC分类号： H01L21336

CPC分类号： H01L27/11502 ,  H01L21/76224 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/10873 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/78391 ,  Y10S257/903

摘要： A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.

摘要翻译： 第一绝缘膜和第一多晶硅膜形成在半导体衬底的第一和第二元件区上。 从第二元件区域去除第一绝缘膜和第一多晶硅膜。 在除去第一绝缘膜和第一多晶硅膜的第二元件区域上形成第二绝缘膜，在第二绝缘膜上形成第二多晶硅膜。 处理第一多晶硅膜，在第一元件区域形成第一栅电极。 处理第二多晶硅膜，在第二元件区域形成第二栅电极。 从元件隔离区域去除氮化硅膜。 在去除了氮化硅膜的区域上形成金属膜，并且连接第一和第二栅电极。

公开(公告)号：US5698881A

公开(公告)日：1997-12-16

申请号：US353240

申请日：1994-12-02

申请人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

发明人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/0338 ,  H01L21/2255 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66628

摘要： A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

摘要翻译： MOS型半导体器件具有长度为170nm（0.17μm）以下的栅极，沟道附近的源极和漏极扩散层的结深度为22nm以下，表面上的杂质浓度 在源极和漏极扩散层中形成1020cm-3以上。 这种结构使用从950℃到1050℃的热范围的固相扩散和/或通过灰化或蚀刻使栅极宽度变窄来获得。 其他MOS型半导体器件的特征在于源极和漏极扩散层区域中的结深度xj [nm]与有效沟道长度Leff [nm]之间的关系由Leff> 0.69×j-6.17确定。

公开(公告)号：US5032890A

公开(公告)日：1991-07-16

申请号：US302960

申请日：1989-01-30

申请人： Yukihiro Ushiku ,  Takashi Mitsuhashi

发明人： Yukihiro Ushiku ,  Takashi Mitsuhashi

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5283 ,  H01L23/5222 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device including a semiconductor substrate, a lower interconnection layer pattern formed along first parallel lines on the substrate, an insulating layer formed on the pattern, and an upper interconnection layer pattern formed along second parallel lines perpendicularly intersecting with the first parallel lines on the insulating layer. A dummy pattern made of the same material as that of the lower interconnection layer pattern, and not electrically connected to the upper and lower interconnection layer patterns, is formed in a region which is arranged below the upper interconnection layer pattern and in which the first parallel lines intersect the second parallel lines. The dummy pattern has the same level as that of the lower interconnection layer pattern, has no lower interconnection layer pattern, and is adjacent to the lower interconnection layer pattern, at a predetermined interval from the lower interconnection layer pattern. By arranging such a dummy pattern, the insulating layer formed on the lower interconnection layer is flattened, thereby preventing disconnection of the upper interconnection layer.

摘要翻译： 一种半导体集成电路器件，包括半导体衬底，沿着衬底上的第一平行线形成的下互连层图案，形成在图案上的绝缘层，以及沿与第一平行线垂直相交的第二平行线形成的上互连层图案 在绝缘层上。 在与上部互连层图案的上方配置的区域形成由与下部布线层图案相同材料构成的虚拟图案，并且不与上部和下部布线层图案电连接， 线与第二条平行线相交。 虚拟图案与下部互连层图案的层次相同，与下部互连层图案以预定的间隔没有较低的互连层图案，并且与下部布线层图案相邻。 通过布置这样的虚设图案，形成在下互连层上的绝缘层变平，从而防止上互连层的断开。