公开(公告)号：US12002807B2

公开(公告)日：2024-06-04

申请号：US17844081

申请日：2022-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jing-Jung Huang ,  Ching En Chen ,  Jung-Hui Kao ,  Kong-Beng Thei

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66681 ,  H01L29/7816

Abstract: A semiconductor structure includes a substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region; a first isolation disposed in the first region, wherein the first isolation is between a first source and a first drain, a first spacer overlaps the first isolation, the first isolation is separated from the first spacer by a first gate dielectric.

公开(公告)号：US11996317B2

公开(公告)日：2024-05-28

申请号：US17150490

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Kai Hsiao ,  Han-De Chen ,  Tsai-Yu Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/28008 ,  H01L21/76227 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/0649

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

公开(公告)号：US11990511B2

公开(公告)日：2024-05-21

申请号：US17458950

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I Kuo ,  Wei Hao Lu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/94 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.

公开(公告)号：US11990375B2

公开(公告)日：2024-05-21

申请号：US17852716

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Jaming Chang ,  Kai Hung Cheng ,  Chia-Hui Lin ,  Jei Ming Chen

IPC: H01L27/148 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

公开(公告)号：US11990341B2

公开(公告)日：2024-05-21

申请号：US17818600

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Uei Jang ,  Ya-Yi Tsai ,  Ryan Chia-Jen Chen ,  An Chyi Wei ,  Shu-Yuan Ku

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/02164 ,  H01L21/32135 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

公开(公告)号：US20240162227A1

公开(公告)日：2024-05-16

申请号：US18513619

申请日：2023-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guan-Lin CHEN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Jung-Chien CHENG ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823412

Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.

公开(公告)号：US20240162094A1

公开(公告)日：2024-05-16

申请号：US18405040

申请日：2024-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Chuan CHIU ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Chun-Yuan CHEN ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

公开(公告)号：US20240153947A1

公开(公告)日：2024-05-09

申请号：US18412236

申请日：2024-01-12

Applicant: Intel Corporation

Inventor： Byron HO ,  Chun-Kuo HUANG ,  Erica THOMPSON ,  Jeanne LUCE ,  Michael L. HATTENDORF ,  Christopher P. AUTH ,  Ebony L. MAYS

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

公开(公告)号：US11978724B2

公开(公告)日：2024-05-07

申请号：US18145375

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L21/82 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H10B99/00

CPC classification number: H01L25/0657 ,  H01L21/02532 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L23/528 ,  H01L25/50 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H10B99/00 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US11972981B2

公开(公告)日：2024-04-30

申请号：US17807645

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Ying-Keung Leung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.