-
公开(公告)号：US20190181003A1
公开(公告)日：2019-06-13
申请号：US16324859
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Jeanne L. LUCE , Ebony L. MAYS , Aravind S. KILLAMPALLI , Jay P. GUPTA
CPC classification number: H01L21/02271 , C23C16/56 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02219 , H01L21/02263 , H01L21/02274 , H01L21/02321 , H01L21/02326 , H01L21/02329 , H01L21/02337 , H01L21/205 , H01L21/76828 , H01L21/76837 , H01L23/147 , H01L23/49827 , H01L23/5383
Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.
-
公开(公告)号：US20210035972A1
公开(公告)日：2021-02-04
申请号：US17076425
申请日：2020-10-21
Applicant: Intel Corporation
Inventor： Byron HO , Chun-Kuo HUANG , Erica THOMPSON , Jeanne LUCE , Michael L. HATTENDORF , Christopher P. AUTH , Ebony L. MAYS
IPC: H01L27/088 , H01L29/66 , H01L21/762 , H01L29/06 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L27/092
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.
-
公开(公告)号：US20240249972A1
公开(公告)日：2024-07-25
申请号：US18590747
申请日：2024-02-28
Applicant: Intel Corporation
Inventor： Ebony L. MAYS , Bruce J. TUFTS
IPC: H01L21/762 , H01L21/02 , H01L29/06
CPC classification number: H01L21/76224 , H01L21/02271 , H01L21/0228 , H01L21/02282 , H01L29/0649
Abstract: Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.
-
公开(公告)号：US20220262795A1
公开(公告)日：2022-08-18
申请号：US17736029
申请日：2022-05-03
Applicant: Intel Corporation
Inventor： Byron HO , Chun-Kuo HUANG , Erica THOMPSON , Jeanne LUCE , Michael L. HATTENDORF , Christopher P. AUTH , Ebony L. MAYS
IPC: H01L27/088 , H01L29/66 , H01L21/762 , H01L29/06 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L27/092
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.
-
公开(公告)号：US20240153947A1
公开(公告)日：2024-05-09
申请号：US18412236
申请日：2024-01-12
Applicant: Intel Corporation
Inventor： Byron HO , Chun-Kuo HUANG , Erica THOMPSON , Jeanne LUCE , Michael L. HATTENDORF , Christopher P. AUTH , Ebony L. MAYS
IPC: H01L27/088 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/66 , H01L29/78
CPC classification number: H01L27/0886 , H01L21/76232 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0653 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/66818 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/7851
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.
-
公开(公告)号：US20230128779A1
公开(公告)日：2023-04-27
申请号：US18088467
申请日：2022-12-23
Applicant: Intel Corporation
Inventor： Ebony L. MAYS , Bruce J. TUFTS
IPC: H01L21/762 , H01L21/02 , H01L29/06
Abstract: Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.
-
公开(公告)号：US20200321333A1
公开(公告)日：2020-10-08
申请号：US16906680
申请日：2020-06-19
Applicant: Intel Corporation
Inventor： Byron HO , Chun-Kuo HUANG , Erica THOMPSON , Jeanne LUCE , Michael L. HATTENDORF , Christopher P. AUTH , Ebony L. MAYS
IPC: H01L27/088 , H01L29/66 , H01L21/762 , H01L29/06 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L27/092
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.
-
公开(公告)号：US20200058761A1
公开(公告)日：2020-02-20
申请号：US16342865
申请日：2016-12-02
Applicant: Intel Corporation
Inventor： Byron HO , Michael L. HATTENDORF , Jeanne L. LUCE , Ebony L. MAYS , Erica J. THOMPSON
IPC: H01L29/66 , H01L21/768 , H01L29/78 , H01L29/08 , H01L27/092 , H01L21/8234 , H01L21/762
Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.
