公开(公告)号：US12009391B2

公开(公告)日：2024-06-11

申请号：US17341034

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions, the gate structure including: a gate dielectric material around each of the nanosheets; a work function material around the gate dielectric material; a liner material around the work function material, where the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along sidewalls of the nanosheets; and a gate electrode material around at least portions of the liner material.

公开(公告)号：US12009264B2

公开(公告)日：2024-06-11

申请号：US17838785

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/51 ,  C23C16/34 ,  C23C16/455 ,  H01L21/28 ,  H01L21/285 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.

公开(公告)号：US20240113183A1

公开(公告)日：2024-04-04

申请号：US18525521

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

公开(公告)号：US11948981B2

公开(公告)日：2024-04-02

申请号：US17405406

申请日：2021-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78645

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

公开(公告)号：US11901362B2

公开(公告)日：2024-02-13

申请号：US17884052

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US11855098B2

公开(公告)日：2023-12-26

申请号：US17986379

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L27/092 ,  H01L21/324 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/321 ,  H01L21/027 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/02318 ,  H01L21/02321 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/517 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7851 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7848

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US20230282729A1

公开(公告)日：2023-09-07

申请号：US17662545

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chun-Da Liao ,  Cheng-Lung Hung ,  Yan-Ming Tsai ,  Harry Chien ,  Huang-Lin Chao ,  Weng Chang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/41791

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

公开(公告)号：US20230207663A1

公开(公告)日：2023-06-29

申请号：US17662685

申请日：2022-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0665 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/4966 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interfacial layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interfacial layer. The dipole layer includes metal atoms. Fluorine atoms are incorporated in the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interfacial layer. The dipole layer is removed.

公开(公告)号：US11646311B2

公开(公告)日：2023-05-09

申请号：US16676443

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/82345 ,  H01L21/823431

Abstract: A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.

公开(公告)号：US20220336285A1

公开(公告)日：2022-10-20

申请号：US17809944

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.